Abstract: A cross-site shopping server and cross-site shopping method is related to a cross-site shopping server including an inventory database and a web-based dynamic-object generating module. The inventory database storages the inventory-information of the products in a plurality of product webpages of at least one company server. Each of the inventory-information includes an inventory-product-name and an allowable sale number. The web-based dynamic object generating module generates web-based dynamic objects for each of the company servers. The web-based dynamic object searches the inventory database to obtain the allowable sale number, so as to calculate an allowable buying number. The company servers inset a connecting address corresponding to the web-based dynamic object into all the product webpages. Therefore, when connecting to the product webpage, a consumer end loads the web-based dynamic object through the connecting address so that the allowable buying number is displayed on the product webpage.

Abstract: An amplitude modulation circuit in a polar transmitter includes a digital-to-analog converter (DAC), a filter, a gm stage, and a calibration module. The DAC is arranged to be coupled to an amplitude modulation signal input in a normal mode. The filter is coupled to the DAC, and the gm stage is coupled to the filter. The calibration module has an input coupled to the gm stage, and an output coupled to a node on a path between the DAC and the gm stage. A method for calibrating an amplitude offset in the polar transmitter includes: generating an amplitude offset calibration signal according to an amplitude modulation signal generated from the gm stage; and transmitting the amplitude offset calibration signal via the output of the calibration module to a node on a path between the DAC and the gm stage so as to calibrate the amplitude offset.

Abstract: An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.

Abstract: An amplitude modulation circuit in a polar transmitter includes a digital-to-analog converter (DAC), a filter, a gm stage, and a calibration module. The DAC is arranged to be coupled to an amplitude modulation signal input in a normal mode. The filter is coupled to the DAC, and the gm stage is coupled to the filter. The calibration module has an input coupled to the gm stage, and an output coupled to a node on a path between the DAC and the gm stage. A method for calibrating an amplitude offset in the polar transmitter includes: generating an amplitude offset calibration signal according to an amplitude modulation signal generated from the gm stage; and transmitting the amplitude offset calibration signal via the output of the calibration module to a node on a path between the DAC and the gm stage so as to calibrate the amplitude offset.

Abstract: An amplitude modulation circuit in a polar transmitter and a method for calibrating amplitude offset in the polar transmitter are provided. The amplitude modulation circuit includes a digital-to-analog converter (DAC), a low pass filter (LPF), a gm stage, and a calibration module. The DAC is coupled to an amplitude modulation signal input. The LPF is coupled to the DAC, and the gm stage is coupled to the LPF. The calibration module has an input coupled to the gm stage, and an output coupled to a node on a path between the DAC and the gm stage. The method includes: generating an amplitude offset calibration signal according to an amplitude modulation signal generated from the gm stage; and transmitting the amplitude offset calibration signal via the output of the calibration module to a node on a path between the DAC and the gm stage so as to calibrate the amplitude offset.

Abstract: An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.

Abstract: A load device has tunable capacitive units including at least a first tunable capacitive unit and a second tunable capacitive unit with different inherent capacitive characteristics, respectively. Each of the first tunable capacitive unit and the second tunable capacitive unit has a first node and a second node, where the first nodes of the first tunable capacitive unit and the second tunable capacitive unit are coupled to a first voltage, the second node of the first tunable capacitive unit is coupled to a second voltage, and the second node of the second tunable capacitive unit is coupled to a third voltage.

Abstract: A buffering circuit includes: a first transistor having a gate terminal coupled to an input signal for buffering the input signal to generate an output signal under an operating current, a second transistor cascoded with the first transistor for generating the operating current for the first transistor according to a control signal at a gate terminal of the second transistor, and a control circuit having a first terminal coupled to the gate terminal of the first transistor and a second terminal coupled to a reference source. The control circuit adjusts the control signal according to the input signal and the reference source, wherein when a voltage level of the input signal varies, the control circuit is arranged to adjust a voltage level of the control signal such that the adjusted voltage level of the control signal varies inversely proportional to the varied voltage level of the input signal.

Abstract: An amplitude modulation circuit in a polar transmitter and a method for calibrating amplitude offset in the polar transmitter are provided. The amplitude modulation circuit includes a digital-to-analog converter (DAC), a low pass filter (LPF), a gm stage, and a calibration module. The DAC is coupled to an amplitude modulation signal input. The LPF is coupled to the DAC, and the gm stage is coupled to the LPF. The calibration module has an input coupled to the gm stage, and an output coupled to a node on a path between the DAC and the gm stage. The method includes: generating an amplitude offset calibration signal according to an amplitude modulation signal generated from the gm stage; and transmitting the amplitude offset calibration signal via the output of the calibration module to a node on a path between the DAC and the gm stage so as to calibrate the amplitude offset.

Abstract: A signal processing apparatus includes sample and hold units for holding a plurality of analog photo diode signals. A signal holding controller generates control signals to the sample and hold units for holding the analog photo diode signals. Analog adjusting modules adjust the held analog photo diode signals. A multiplexer selectively couples one input end of the multiplexer to the output end of the multiplexer for outputting the adjusted analog photo diode signals. An analog to digital converter converts the adjusted analog photo diode signals into digital photo diode signals.

Abstract: A laser power control system and related method for reducing a settling time in a target laser power transition are disclosed. The laser power control system includes a state decision circuit, for generating a state decision signal according to a selected operational state of a target circuit; a plurality of buffers, for storing a plurality of control data corresponding to a plurality of candidate operational states of the target circuit respectively; and a multiplexer, coupled between the state decision circuit and the buffers, for coupling a selected buffer of the buffers and the target circuit according to the state decision signal for outputting a control datum stored in the selected buffer to the target circuit.

Abstract: A method for controlling a specific output power level emitted from a laser diode (LD) in an optical pick-up head unit (OPU) is disclosed. The LD is configured to provide a plurality of output power levels for accessing/recording an optical disc. The method includes: determining a specific power control value according to a first output power level, a second output power level, a first power control value of the first output power level, and the specific output power level, wherein the first output power level is less than the specific output power level and greater than the second output power level; and driving the LD to emit the specific output power level according to the specific power control value, the first power control value, and a second power control value of the second output power level.

Abstract: A high-to-low level shifter is disclosed, comprising a high voltage unit and a low voltage unit. The high voltage unit receives an input signal from an input node. The high voltage unit outputs a first output signal to an output node when the high voltage unit receives a low-voltage-level input signal. The low voltage unit outputs a second output signal to the output node when the high voltage unit receives a high-voltage-level input signal.

Abstract: In a method and apparatus for enabling fast clock phase locking in a phase-locked loop, a sampling clock generator generates sampling clock signals in response to an oscillator output of the phase-locked loop. A detector unit samples an input digital signal to the phase-locked loop at clock edges of the sampling clock signals to obtain multiple sampling points of the input digital signal, and compares logic levels of each temporally adjacent pair of the sampling points to detect presence of a logic level transition in the input digital signal. A selector unit is controlled by the detector unit to select one of the sampling clock signals, which has one of the clock edges thereof defining an interval that was detected to have occurrence of the logic level transition in the input digital signal, and which is subsequently provided to the phase-locked loop as an input phase-locking clock signal.

Abstract: In a method and apparatus for enabling fast clock phase locking in a phase-locked loop, a sampling clock generator generates sampling clock signals in response to an oscillator output of the phase-locked loop. A detector unit samples an input digital signal to the phase-locked loop at clock edges of the sampling clock signals to obtain multiple sampling points of the input digital signal, and compares logic levels of each temporally adjacent pair of the sampling points to detect presence of a logic level transition in the input digital signal. A selector unit is controlled by the detector unit to select one of the sampling clock signals, which has one of the clock edges thereof defining an interval that was detected to have occurrence of the logic level transition in the input digital signal, and which is subsequently provided to the phase-locked loop as an input phase-locking clock signal.