Patents by Inventor Jong Wook Ju

Jong Wook Ju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8956914
    Abstract: An integrated circuit package system comprising: forming a substrate having a solder mask with a support structure formed from the solder mask; mounting a first integrated circuit device over the support structure; connecting the substrate and the first integrated circuit device; and encapsulating the first integrated circuit device and the support structure.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: February 17, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Ja Eun Yun, Jong Wook Ju
  • Patent number: 8659175
    Abstract: An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit device with the first internal interconnect within the adhesive spacer, connecting a second internal interconnect between the carrier and the second integrated circuit device, and encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 25, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Jong Wook Ju, Taeg Ki Lim, Hyun Joung Kim
  • Patent number: 8632112
    Abstract: A method of operation of a workpiece displacement system includes: providing a head including a conduit, a recess port, and a channel, the conduit configured such that its major axis intersects the recess port and the channel; inserting a force distribution member into the recess port; and supplying a negative pressure state through the head and the force distribution member.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Hyunjoo Kim, Hunki Lee, Changyong Lee, Jong Wook Ju, Sang-Ho Lee
  • Patent number: 8623704
    Abstract: An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands (52, 52A) securing the first and second die to one another at a chosen separation (53). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: January 7, 2014
    Assignee: CHIPPAC, Inc.
    Inventors: Sang Ho Lee, Jong Wook Ju, Hyeog Chan Kwon
  • Patent number: 8617924
    Abstract: A method of manufacture of a stacked integrated circuit package-in-package system includes forming a substrate with a top contact, mounting a first device having a first terminal over the substrate, stacking a second device having a second terminal over the first device in an offset configuration, connecting the first terminal to the top contact below the first terminal, and connecting the second terminal to the top contact below the second terminal.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: December 31, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: OhSug Kim, Jong-Woo Ha, Jong Wook Ju
  • Patent number: 8569882
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a central integrated circuit over the base substrate; mounting a side package having a side package substrate along a peripheral region of the base substrate and laterally peripheral to the central integrated circuit with the side package substrate coplanar with the central integrated circuit; and encapsulating the central integrated circuit and the side package above the base substrate with a base encapsulation to form a planar surface over the central integrated circuit and the side package facing away from the base substrate.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: October 29, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: WonJun Ko, Sungmin Song, Jong Wook Ju, JaEun Yun, Hye Ran Lee
  • Patent number: 8552551
    Abstract: Adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device in a stacked semiconductor assembly, include a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate or so that the die attach side of the upper package faces away from the lower die or lower package substrate.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: October 8, 2013
    Assignee: CHIPPAC, Inc.
    Inventors: Sang Ho Lee, Jong Wook Ju, Hyeog Chan Kwon, Marcos Karnezos
  • Patent number: 8415204
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate; mounting an integrated circuit die on the package substrate; and attaching a heat spreader assembly, having a thermal adhesive layer formed therein, to the package substrate and the integrated circuit die.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: April 9, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: JaEun Yun, Jong Wook Ju, WonJun Ko, Hye Ran Lee
  • Publication number: 20120241980
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a central integrated circuit over the base substrate; mounting a side package having a side package substrate along a peripheral region of the base substrate and laterally peripheral to the central integrated circuit with the side package substrate coplanar with the central integrated circuit; and encapsulating the central integrated circuit and the side package above the base substrate with a base encapsulation to form a planar surface over the central integrated circuit and the side package facing away from the base substrate.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Inventors: WonJun Ko, Sungmin Song, Jong Wook Ju, JaEun Yun, Hye Ran Lee
  • Publication number: 20120224332
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate; a first module attached to the substrate; a conductive connection built on the first module and conductively connected thereto; an adhesive spacer on the first module with the conductive connection exposed; and a second module on the adhesive spacer in conductive contact with the conductive connection and partially supported thereby.
    Type: Application
    Filed: March 2, 2011
    Publication date: September 6, 2012
    Inventors: JaEun Yun, Jong Wook Ju
  • Patent number: 8217501
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts; attaching an integrated circuit to the top surface; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that are over and larger than the electrical contacts.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: July 10, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Hyeog Chan Kwon, Hyun Joung Kim, Jae Chang Kim, Taeg Ki Lim, Jong Wook Ju
  • Patent number: 8143102
    Abstract: An integrated circuit package system includes: providing a substrate; attaching a base die to the substrate, the base die having a relief region with a shaped cross-section; and connecting a bond wire between an active base surface of the base die and the substrate, the bond wire extending through the shaped cross-section of the relief region.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: March 27, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Sang-Ho Lee, Jong Wook Ju
  • Patent number: 8067275
    Abstract: An integrated circuit package system comprising: providing a base substrate; attaching a base integrated circuit die over the base substrate; forming a support over the base substrate near only one edge of the base substrate; and attaching a stack substrate over the support and the base integrated circuit die.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: WonJun Ko, Jong Wook Ju, SeungYong Chai, Taeg Ki Lim, Ja Eun Yun
  • Patent number: 8067831
    Abstract: An integrated circuit package system is provided including forming a first substrate, mounting a first integrated circuit to the first substrate, and forming first planar interconnects in contact with the first integrated circuit and electrically connecting the first integrated circuit to the first substrate.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Hyeog Chan Kwon, Tae Sung Jeong, Jae Han Chung, Taeg Ki Lim, Jong Wook Ju
  • Publication number: 20100244236
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate; mounting an integrated circuit die on the package substrate; and attaching a heat spreader assembly, having a thermal adhesive layer formed therein, to the package substrate and the integrated circuit die.
    Type: Application
    Filed: March 26, 2009
    Publication date: September 30, 2010
    Inventors: JaEun Yun, Jong Wook Ju, WonJun Ko, Hye Ran Lee
  • Publication number: 20100237488
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts; attaching an integrated circuit to the top surface; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that are over and larger than the electrical contacts.
    Type: Application
    Filed: May 28, 2010
    Publication date: September 23, 2010
    Inventors: Hyeog Chan Kwon, Hyun Joung Kim, Jae Chang Kim, Taeg Ki Lim, Jong Wook Ju
  • Patent number: 7772683
    Abstract: A stacked integrated circuit package-in-package system is provided including forming a substrate having a top surface and a bottom surface, mounting a first device over the top surface, stacking a second device over the first device in an offset configuration, connecting a first internal interconnect between the first device and the bottom surface, connecting a second internal interconnect between the second device and the bottom surface, and encapsulating the first device and the second device.
    Type: Grant
    Filed: December 9, 2006
    Date of Patent: August 10, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Ki Youn Jang, Jong-Woo Ha, Jong Wook Ju
  • Patent number: 7763961
    Abstract: A hybrid stacking package system is provided including providing a board-on-chip substrate, having an opening, attaching a first integrated circuit on the board-on-chip substrate, attaching bond wires, between the first integrated circuit and the board-on-chip substrate, through the opening, and mounting a second integrated circuit over the bond wires.
    Type: Grant
    Filed: April 1, 2006
    Date of Patent: July 27, 2010
    Assignee: STATS ChipPAC Ltd.
    Inventors: Seung Wook Park, Jong Wook Ju
  • Patent number: 7737539
    Abstract: An integrated circuit package system including a substrate with a top surface and a bottom surface. Configuring the top surface to include electrical contacts formed between a perimeter of the substrate and a semiconductor die. Aligning over the top surface of the substrate a mold plate with a honeycomb meshwork of posts or a stepped honeycomb meshwork of posts and depositing a material to prevent warpage of the substrate between the top surface of the substrate and the mold plate. Removing the mold plate to reveal discrete hollow conduits formed within the material that align with the electrical contacts.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: June 15, 2010
    Assignee: STATS Chippac Ltd.
    Inventors: Hyeog Chan Kwon, Hyun Joung Kim, Jae Chang Kim, Taeg Ki Lim, Jong Wook Ju
  • Publication number: 20100044849
    Abstract: A method of manufacture of a stacked integrated circuit package-in-package system includes forming a substrate with a top contact, mounting a first device having a first terminal over the substrate, stacking a second device having a second terminal over the first device in an offset configuration, connecting the first terminal to the top contact below the first terminal, and connecting the second terminal to the top contact below the second terminal.
    Type: Application
    Filed: November 4, 2009
    Publication date: February 25, 2010
    Inventors: OhSug Kim, Jong-Woo Ha, Jong Wook Ju