Abstract: A capacitor component includes a body including dielectric layers, first and second internal electrodes, laminated in a first direction, facing each other, and first and second cover portions, disposed on outermost portions of the first and second internal electrodes, and first and second external electrodes, respectively disposed on both external surfaces of the body in a second direction, perpendicular to the first direction, and respectively connected to the first and second internal electrodes. An indentation including a glass is disposed at at least one of boundaries between the first internal electrodes and the first external electrode or one of boundaries between the second internal electrodes and the second external electrode.

Abstract: A three-dimensional (3D) semiconductor memory device comprises memory cell strings each comprising at least one selection transistor and at least one memory cell, a first pass transistor group sharing a first well region and comprising a first selection line pass transistor connected to the selection transistor and a first world line pass transistor connected to the memory cell, a second pass transistor group sharing a second well region and comprising a second selection line pass transistor connected to the selection transistor, and a controller that controls the first pass transistor group and the second pass transistor group. The controller applies selected voltages to the first and second well regions during read operation.

Abstract: A three-dimensional (3D) semiconductor memory device comprises memory cell strings each comprising at least one selection transistor and at least one memory cell, a first pass transistor group sharing a first well region and comprising a first selection line pass transistor connected to the selection transistor and a first world line pass transistor connected to the memory cell, a second pass transistor group sharing a second well region and comprising a second selection line pass transistor connected to the selection transistor, and a controller that controls the first pass transistor group and the second pass transistor group. The controller applies selected voltages to the first and second well regions during read operation.

Abstract: A nonvolatile memory device for preventing program disturbances includes a memory cell array block, a word line driver, and a well bias control unit. The memory cell array block includes at least one cell string having a plurality of memory cells serially connected to a bit line and alternately connected to even word lines and odd word lines. After a program verification, the word line driver drives the even word lines with a first voltage and then the odd word lines with the first voltage to drop the even word line to a voltage lower than the first voltage. The well bias control unit floats a bias of a p-well formed by high voltage NMOS transistors that apply corresponding driving voltages to the even word lines and the odd word lines according to an operation mode of a program operation, a read operation, and an erase operation.

Abstract: A nonvolatile memory device for preventing program disturbances includes a memory cell array block, a word line driver, and a well bias control unit. The memory cell array block includes at least one cell string having a plurality of memory cells serially connected to a bit line and alternately connected to even word lines and odd word lines. After a program verification, the word line driver drives the even word lines with a first voltage and then the odd word lines with the first voltage to drop the even word line to a voltage lower than the first voltage. The well bias control unit floats a bias of a p-well formed by high voltage NMOS transistors that apply corresponding driving voltages to the even word lines and the odd word lines according to an operation mode of a program operation, a read operation, and an erase operation.

Abstract: A nonvolatile memory device for preventing program disturbances includes a memory cell array block, a word line driver, and a well bias control unit. The memory cell array block includes at least one cell string having a plurality of memory cells serially connected to a bit line and alternately connected to even word lines and odd word lines. After a program verification, the word line driver drives the even word lines with a first voltage and then the odd word lines with the first voltage to drop the even word line to a voltage lower than the first voltage. The well bias control unit floats a bias of a p-well formed by high voltage NMOS transistors that apply corresponding driving voltages to the even word lines and the odd word lines according to an operation mode of a program operation, a read operation, and an erase operation.

Abstract: In a flash memory device, different self-boosting techniques are selectively applied to a string of serially connected memory cells responsive to a programming voltage applied to a selected word line. For example, non-local self-boosting and local self-boosting may be selectively applied responsive to the programming voltage applied to the selected word line. For example, non-local self-boosting and local self-boosting may be selectively applied to a first string of serially-connected cells responsive to the programming voltage during an incremental step pulse programming (ISPP) of a selected cell of a second string of serially-connected cells.

Abstract: A method of performing an erase operation in a non-volatile memory device includes a multi-erase operation and a post-erase operation. The multi-erase operation includes multi-erasing multiple memory blocks at the same time using a multi-erase voltage. The post-erase operation includes post-erasing one or more failed memory blocks of the multi-erased memory blocks using a post-erase voltage having sequentially increasing voltage values based on incremental step pulses (ISPs).

Abstract: A non-volatile semiconductor memory device includes a page buffer comprising a lower latch block and an upper latch block, and a memory array that is connected to the lower latch block via a lower common bit line and that is connected to the upper latch block via an upper common bit line. The memory array includes a plurality of non-volatile memory cells, a lower even bit line and a lower odd bit line that are selectively connectable to the lower common bit line, an upper even bit line and an upper odd bit line that are selectively connectable to the upper common bit line, a first switch that electrically connects the lower even bit line to the upper even bit line in response to a first connection control signal and a second switch that electrically connects the lower odd bit line to the upper odd bit line in response to a second connection control signal.

Abstract: A nonvolatile memory device for preventing program disturbances includes a memory cell array block, a word line driver, and a well bias control unit. The memory cell array block includes at least one cell string having a plurality of memory cells serially connected to a bit line and alternately connected to even word lines and odd word lines. After a program verification, the word line driver drives the even word lines with a first voltage and then the odd word lines with the first voltage to drop the even word line to a voltage lower than the first voltage. The well bias control unit floats a bias of a p-well formed by high voltage NMOS transistors that apply corresponding driving voltages to the even word lines and the odd word lines according to an operation mode of a program operation, a read operation, and an erase operation.

Abstract: A non-volatile semiconductor memory device includes a page buffer comprising a lower latch block and an upper latch block, and a memory array that is connected to the lower latch block via a lower common bit line and that is connected to the upper latch block via an upper common bit line. The memory array includes a plurality of non-volatile memory cells, a lower even bit line and a lower odd bit line that are selectively connectable to the lower common bit line, an upper even bit line and an upper odd bit line that are selectively connectable to the upper common bit line, a first switch that electrically connects the lower even bit line to the upper even bit line in response to a first connection control signal and a second switch that electrically connects the lower odd bit line to the upper odd bit line in response to a second connection control signal.

Abstract: A memory card comprises a memory controller connected to a non-volatile memory module. The memory controller comprises a first circuit adapted to convert a first external address into a first internal address using a program stored in an internal memory. The memory controller further comprises a hardware accelerator adapted to generate a second internal address based on the first internal and external addresses.

Abstract: A method for managing data stored in a non-volatile memory having a plurality of memory blocks includes, first, determining if an error occurs in the read data in a selected memory block. If an error occurs in the read data in the selected memory block, then a region to which the selected memory block belongs is determined. If the selected memory block belongs to a code data region, it is determined if the number of bit errors of the read data is less than or equal to an allowed number of bit errors. If number of bit errors of the read data is less than or equal to the allowed number of bit errors, the selected memory block of the code data region is replaced with a reserved memory block, and the selected memory block of the code data region is designated to a user data region.

Abstract: In a flash memory device, different self-boosting techniques are selectively applied to a string of serially connected memory cells responsive to a programming voltage applied to a selected word line. For example, non-local self-boosting and local self-boosting may be selectively applied responsive to the programming voltage applied to the selected word line. For example, non-local self-boosting and local self-boosting may be selectively applied to a first string of serially-connected cells responsive to the programming voltage during an incremental step pulse programming (ISPP) of a selected cell of a second string of serially-connected cells.

Abstract: A non-volatile semiconductor memory device includes a page buffer comprising a lower latch block and an upper latch block, and a memory array that is connected to the lower latch block via a lower common bit line and that is connected to the upper latch block via an upper common bit line. The memory array includes a plurality of non-volatile memory cells, a lower even bit line and a lower odd bit line that are selectively connectable to the lower common bit line, an upper even bit line and an upper odd bit line that are selectively connectable to the upper common bit line, a first switch that electrically connects the lower even bit line to the upper even bit line in response to a first connection control signal and a second switch that electrically connects the lower odd bit line to the upper odd bit line in response to a second connection control signal.

Abstract: A memory card comprises a memory controller connected to a non-volatile memory module. The memory controller comprises a first circuit adapted to convert a first external address into a first internal address using a program stored in an internal memory. The memory controller further comprises a hardware accelerator adapted to generate a second internal address based on the first internal and external addresses.

Abstract: A method for managing data stored in a non-volatile memory having a plurality of memory blocks includes, first, determining if an error occurs in the read data in a selected memory block. If an error occurs in the read data in the selected memory block, then a region to which the selected memory block belongs is determined. If the selected memory block belongs to a code data region, it is determined if the number of bit errors of the read data is less than or equal to an allowed number of bit errors. If number of bit errors of the read data is less than or equal to the allowed number of bit errors, the selected memory block of the code data region is replaced with a reserved memory block, and the selected memory block of the code data region is designated to a user data region.

Abstract: A refresh circuit having a variable restore time according to an operating mode of a semiconductor memory device and a refresh method of the same is provided. The refresh circuit includes a refresh pulse generating unit for receiving a clock signal to generate first and second refresh signals, a standby refresh signal generating unit for receiving the second refresh signal and a chip select signal to generate a standby refresh signal, the chip select signal representing an active state and a standby state of the semiconductor memory device, and a word-line pulse generating unit for receiving the first refresh signal and the standby refresh signal to generate a word-line driving signal. A pulse width of the word-line driving signal generated at the standby state is longer than that generated at the active state resulting in a sufficient refresh time at each memory cell.

Abstract: A refresh circuit having a variable restore time according to an operating mode of a semiconductor memory device and a refresh method of the same is provided. The refresh circuit includes a refresh pulse generating unit for receiving a clock signal to generate first and second refresh signals, a standby refresh signal generating unit for receiving the second refresh signal and a chip select signal to generate a standby refresh signal, the chip select signal representing an active state and a standby state of the semiconductor memory device, and a word-line pulse generating unit for receiving the first refresh signal and the standby refresh signal to generate a word-line driving signal. A pulse width of the word-line driving signal generated at the standby state is longer than that generated at the active state resulting in a sufficient refresh time at each memory cell.