Patents by Inventor Jong Yuh
Jong Yuh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11906897Abstract: A reflective mask includes a reflective multilayer over a substrate, a capping layer over the reflective multilayer, an absorber layer over the capping layer and including a top surface, and a protection layer directly on the top surface of the absorber layer. The absorber layer is formed of a first material and the protection layer is formed of a second material that is less easily to be oxidized than the first material.Type: GrantFiled: June 17, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Cheng Hsu, Yih-Chen Su, Chi-Kuang Tsai, Ta-Cheng Lien, Tzu Yi Wang, Jong-Yuh Chang, Hsin-Chang Lee
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Publication number: 20220026797Abstract: A pellicle includes a frame configured to attach to a photomask, wherein the frame includes a vent hole. The pellicle further includes a filter covering the vent hole, wherein the filter directly connects to an outer surface of the frame. The pellicle further includes a membrane extending over a top surface of the frame. The pellicle further includes a mount between the frame and the membrane, wherein the mount is attachable to the frame by an adhesive.Type: ApplicationFiled: October 8, 2021Publication date: January 27, 2022Inventors: Chue San YOO, Chih-Chiang TU, Chien-Cheng CHEN, Jong-Yuh CHANG, Kun-Lung HSIEH, Pei-Cheng HSU, Hsin-Chang LEE, Yun-Yue LIN
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Patent number: 11143952Abstract: A method of removing a pellicle from a photomask includes removing a portion of a membrane from a pellicle frame, wherein the pellicle frame remains attached to the photomask following the removing of the portion of the membrane. The method further includes removing the pellicle frame from the photomask. The method further includes cleaning the photomask.Type: GrantFiled: October 31, 2017Date of Patent: October 12, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chue San Yoo, Chih-Chiang Tu, Chien-Cheng Chen, Jong-Yuh Chang, Kun-Lung Hsieh, Pei-Cheng Hsu, Hsin-Chang Lee, Yun-Yue Lin
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Publication number: 20210311383Abstract: A reflective mask includes a reflective multilayer over a substrate, a capping layer over the reflective multilayer, an absorber layer over the capping layer and including a top surface, and a protection layer directly on the top surface of the absorber layer. The absorber layer is formed of a first material and the protection layer is formed of a second material that is less easily to be oxidized than the first material.Type: ApplicationFiled: June 17, 2021Publication date: October 7, 2021Inventors: Pei-Cheng Hsu, Yih-Chen Su, Chi-Kuang Tsai, Ta-Cheng Lien, Tzu Yi Wang, Jong-Yuh Chang, Hsin-Chang Lee
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Patent number: 11048158Abstract: A method comprises receiving a workpiece that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further comprises patterning the absorber layer to provide first trenches corresponding to circuit patterns on a wafer, and patterning the absorber layer, the capping layer, and the reflective multilayer to provide second trenches corresponding to a die boundary area on the wafer, thereby providing an extreme ultraviolet lithography (EUVL) mask. The method further comprises treating the EUVL mask with a treatment chemical that prevents exposed surfaces of the absorber layer from oxidation.Type: GrantFiled: April 18, 2018Date of Patent: June 29, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Cheng Hsu, Yih-Chen Su, Chi-Kuang Tsai, Ta-Cheng Lien, Tzu Yi Wang, Jong-Yuh Chang, Hsin-Chang Lee
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Patent number: 10859906Abstract: The present disclosure describes a method to form alignment marks on or in the top layer of an extreme ultraviolet (EUV) mask blank without the use of photolithographic methods. For example, the method can include forming a metal structure on the top layer of the EUV mask blank by dispensing a hexacarbonylchromium vapor on the top layer of the EUV mask and exposing the hexacarbonylchromium vapor to an electron-beam. The hexacarbonylchromium vapor is decomposed to form the metal structure at an area which is proximate to where the hexacarbonylchromium vapors interact with the electron-beam. In another example, the method can include forming a patterned structure in the top layer of an EUV mask blank with the use of an etcher aperture and an etching process.Type: GrantFiled: July 8, 2019Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yi-Fu Hsieh, Chih-Chiang Tu, Jong-Yuh Chang, Hsin-Chang Lee
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Publication number: 20190332004Abstract: The present disclosure describes a method to form alignment marks on or in the top layer of an extreme ultraviolet (EUV) mask blank without the use of photolithographic methods. For example, the method can include forming a metal structure on the top layer of the EUV mask blank by dispensing a hexacarbonylchromium vapor on the top layer of the EUV mask and exposing the hexacarbonylchromium vapor to an electron-beam. The hexacarbonylchromium vapor is decomposed to form the metal structure at an area which is proximate to where the hexacarbonylchromium vapors interact with the electron-beam. In another example, the method can include forming a patterned structure in the top layer of an EUV mask blank with the use of an etcher aperture and an etching process.Type: ApplicationFiled: July 8, 2019Publication date: October 31, 2019Inventors: Yi-Fu HSIEH, Chih-Chiang TU, Jong-Yuh CHANG, Hsin-Chang LEE
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Publication number: 20190324364Abstract: A method comprises receiving a workpiece that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further comprises patterning the absorber layer to provide first trenches corresponding to circuit patterns on a wafer, and patterning the absorber layer, the capping layer, and the reflective multilayer to provide second trenches corresponding to a die boundary area on the wafer, thereby providing an extreme ultraviolet lithography (EUVL) mask. The method further comprises treating the EUVL mask with a treatment chemical that prevents exposed surfaces of the absorber layer from oxidation.Type: ApplicationFiled: April 18, 2018Publication date: October 24, 2019Inventors: Pei-Cheng Hsu, Yih-Chen Su, Chi-Kuang Tsai, Ta-Cheng Lien, Tzu Yi Wang, Jong-Yuh Chang, Hsin-Chang Lee
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Patent number: 10345695Abstract: The present disclosure describes a method to form alignment marks on or in the top layer of an extreme ultraviolet (EUV) mask blank without the use of photolithographic methods. For example, the method can include forming a metal structure on the top layer of the EUV mask blank by dispensing a hexacarbonylchromium vapor on the top layer of the EUV mask and exposing the hexacarbonylchromium vapor to an electron-beam. The hexacarbonylchromium vapor is decomposed to form the metal structure at an area which is proximate to where the hexacarbonylchromium vapors interact with the electron-beam. In another example, the method can include forming a patterned structure in the top layer of an EUV mask blank with the use of an etcher aperture and an etching process.Type: GrantFiled: March 31, 2017Date of Patent: July 9, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Fu Hsieh, Chih-Chiang Tu, Jong-Yuh Chang, Hsin-Chang Lee
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Patent number: 10255978Abstract: This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.Type: GrantFiled: May 8, 2017Date of Patent: April 9, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Kenneth Louie, Qui Nguyen, Tai-yuan Tseng, Jong Yuh, Ohwon Kwon
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Publication number: 20190094683Abstract: A method of removing a pellicle from a photomask includes removing a portion of a membrane from a pellicle frame, wherein the pellicle frame remains attached to the photomask following the removing of the portion of the membrane. The method further includes removing the pellicle frame from the photomask. The method further includes cleaning the photomask.Type: ApplicationFiled: October 31, 2017Publication date: March 28, 2019Inventors: Chue San YOO, Chih-Chiang TU, Chien-Cheng CHEN, Jong-Yuh CHANG, Kun-Lung HSIEH, Pei-Cheng HSU, Hsin-Chang LEE, Yun-Yue LIN
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Patent number: 10217520Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.Type: GrantFiled: August 24, 2017Date of Patent: February 26, 2019Assignee: SanDisk Technologies LLCInventors: Muhammad Masuduzzaman, Deepanshu Dutta, Jong Yuh
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Patent number: 10157805Abstract: An apparatus for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing, comprising a plurality of gas injectors for admitting a processing gas into an etching chamber. Each gas injector of the plurality of gas injectors is disposed along a track within the etching chamber and moveable along the track. Further, each gas injector is coupled with a throttling valve or nozzle to permit adjustment of processing gas flow rate. A method for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing includes performing a chemical deposition or etch using the plurality of moveable and adjustable gas injectors and measuring the critical dimension uniformity. Adjustments to the location of at least one gas injector or the processing gas flow rate to at least one gas injector are made to increase critical dimension uniformity.Type: GrantFiled: June 10, 2016Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzung-Shiun Lu, Chun-Lang Chen, Shih-Hao Yang, Jong-Yuh Chang
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Patent number: 10156783Abstract: A system and method for repairing a photolithographic mask is provided. An embodiment comprises forming a shielding layer over an absorbance layer on a substrate. Once the shielding layer is in place, the absorbance layer may be repaired using, e.g., an e-beam process to initiate a reaction to repair a defect in the absorbance layer, with the shielding layer being used to shield the remainder of the absorbance layer from undesirable etching during the repair process.Type: GrantFiled: February 27, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufactuing Company, Ltd.Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Boming Hsu, Tran-Hui Shen
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Publication number: 20180322928Abstract: This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.Type: ApplicationFiled: May 8, 2017Publication date: November 8, 2018Inventors: Kenneth Louie, Qui Nguyen, Tai-yuan Tseng, Jong Yuh, Ohwon Kwon
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Patent number: 10115440Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.Type: GrantFiled: June 16, 2017Date of Patent: October 30, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Qui Nguyen, Alexander Chu, Kenneth Louie, Anirudh Amarnath, Jixin Yu, Yen-Lung Jason Li, Tai-Yuan Tseng, Jong Yuh
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Publication number: 20180197586Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.Type: ApplicationFiled: June 16, 2017Publication date: July 12, 2018Applicant: SanDisk Technologies LLCInventors: Qui Nguyen, Alexander Chu, Kenneth Louie, Anirudh Amarnath, Jixin Yu, Yen-Lung Jason Li, Tai-Yuan Tseng, Jong Yuh
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Patent number: 10012899Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.Type: GrantFiled: November 18, 2016Date of Patent: July 3, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chiang Tu, Chun-Lang Chen, Chue San Yoo, Jong-Yuh Chang, Chia-Shiung Tsai, Ping-Yin Liu, Hsin-Chang Lee, Chih-Cheng Lin, Yun-Yue Lin
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Publication number: 20180158531Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.Type: ApplicationFiled: August 24, 2017Publication date: June 7, 2018Applicant: SanDisk Technologies LLCInventors: Muhammad Masuduzzaman, Deepanshu Dutta, Jong Yuh
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Publication number: 20180149963Abstract: The present disclosure describes a method to form alignment marks on or in the top layer of an extreme ultraviolet (EUV) mask blank without the use of photolithographic methods. For example, the method can include forming a metal structure on the top layer of the EUV mask blank by dispensing a hexacarbonylchromium vapor on the top layer of the EUV mask and exposing the hexacarbonylchromium vapor to an electron-beam. The hexacarbonylchromium vapor is decomposed to form the metal structure at an area which is proximate to where the hexacarbonylchromium vapors interact with the electron-beam. In another example, the method can include forming a patterned structure in the top layer of an EUV mask blank with the use of an etcher aperture and an etching process.Type: ApplicationFiled: March 31, 2017Publication date: May 31, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Fu HSIEH, Chih-Chiang TU, Jong-Yuh CHANG, Hsin-Chang LEE