Abstract: A flash memory device and a read method thereof are provided. At a read operation, a sense node of a page buffer is developed while a bitline is developed and data of a selected memory cell is sensed based on the develop result of the sense node. For a develop period, voltage loss arising from the sense node is compensated fast and the compensated result is latched, which makes it possible to simplify the design and reduce a chip size.

Abstract: A flash memory device includes memory cells, a common node, a sense node connected to a selected bit line, a first register connected to the common node, a second register connected to the common node and the sense node, a common sense circuit connected to the common node, the sense node, and a control node; a switch, and a pre-charge circuit connected to the control node and configured to pre-charge the control node.

Abstract: A page buffer may comprise of a latch connected to a sense node at a first contact point. The page buffer may also comprise of a sensing circuit connected to the sense node at a second contact point, the sensing circuit being configured to sense cell data of the sense node. The page buffer may also comprise of a switch circuit which electrically connects the first contact point with the second contact point after the first contact point is charged by the latch.

Abstract: In one aspect, a non-volatile memory device includes a non-volatile memory cell array and a page buffer. The page buffer includes a sense node selectively connected to a bit line of the memory cell array, a main latch circuit including first and second main latch nodes, where the first main latch node is selectively connected to the sense node, and a latch input node selectively connected to the first and second main latch nodes. The page buffer further includes a cache latch circuit including first and second cache latch nodes, a switching circuit which selectively connects the second cache latch node to the latch input node, and a shared sense circuit connected between to the latch input node and a reference potential. The shared sense circuit selectively connects the latch input node to the reference potential in response to a voltage of the sense node and a voltage of the first cache latch node.

Abstract: A page buffer may comprise of a latch connected to a sense node at a first contact point. The page buffer may also comprise of a sensing circuit connected to the sense node at a second contact point, the sensing circuit being configured to sense cell data of the sense node. The page buffer may also comprise of a switch circuit which electrically connects the first contact point with the second contact point after the first contact point is charged by the latch.

Abstract: A flash memory device is disclosed that comprises memory cells, a common node, a sense node connected to a selected bit line, a first register connected to the common node, and a second register connected to the common node and the sense node. The flash memory device further comprises a common sense circuit connected to the common node, the sense node, and a control node; a switch, and a pre-charge circuit connected to the control node and configured to pre-charge the control node.

Abstract: In one aspect, a non-volatile memory device includes a non-volatile memory cell array and a page buffer. The page buffer includes a sense node selectively connected to a bit line of the memory cell array, a main latch circuit including first and second main latch nodes, where the first main latch node is selectively connected to the sense node, and a latch input node selectively connected to the first and second main latch nodes. The page buffer further includes a cache latch circuit including first and second cache latch nodes, a switching circuit which selectively connects the second cache latch node to the latch input node, and a shared sense circuit connected between to the latch input node and a reference potential. The shared sense circuit selectively connects the latch input node to the reference potential in response to a voltage of the sense node and a voltage of the first cache latch node.

Abstract: In a flash memory device following precharge, a bitline and a sense node are coupled and then developed. A voltage apparent at the sense node is detected to recognize a data value of a corresponding memory cell. For a develop period, a bitline-side capacitance is much higher than a capacitance between adjacent sense nodes.

Abstract: A flash memory device and a read method thereof are provided. At a read operation, a sense node of a page buffer is developed while a bitline is developed and data of a selected memory cell is sensed based on the develop result of the sense node. For a develop period, voltage loss arising from the sense node is compensated fast and the compensated result is latched, which makes it possible to simplify the design and reduce a chip size.

Abstract: An integrated circuit device includes a semiconductor substrate having an interlayer insulating layer thereon and a first junction block embedded in the interlayer insulating layer. The first junction block includes a first plurality of conductive junction traces located side-by-side within the interlayer insulating layer and a corresponding first plurality of pairs of conductive vias connected to opposite ends of respective ones of the first plurality of conductive junction traces. The first junction block also includes a dummy conductive trace located adjacent the first plurality of conductive junction traces and a pair of dummy conductive vias connected to opposite ends of the dummy junction trace. The integrated circuit device further includes a plurality of upper metallization traces routed on the interlayer insulating layer.

Abstract: An integrated circuit device includes a semiconductor substrate having an interlayer insulating layer thereon and a first junction block embedded in the interlayer insulating layer. The first junction block includes a first plurality of conductive junction traces located side-by-side within the interlayer insulating layer and a corresponding first plurality of pairs of conductive vias connected to opposite ends of respective ones of the first plurality of conductive junction traces. The first junction block also includes a dummy conductive trace located adjacent the first plurality of conductive junction traces and a pair of dummy conductive vias connected to opposite ends of the dummy junction trace. The integrated circuit device further includes a plurality of upper metallization traces routed on the interlayer insulating layer.