Abstract: A button-type secondary battery includes a lower can having a bottom surface; an upper can having a top, the upper can and the lower can being coupled to define a space therein; an electrolyte in the space; an electrode assembly in the space and including a negative electrode, a separator, and a positive electrode wound together; a gasket between the upper can and the lower can to electrically insulate the upper and lower cans; a top insulator that is electrically insulating and covering a top surface of the electrode assembly; and a bottom insulator that is electrically insulating and covering a bottom surface of the electrode assembly. The top and bottom insulators are each configured to expand in volume by absorbing the electrolyte. Surfaces of at least one of the top insulator and the bottom insulator are coated with a protective layer to prevent thermal shrinkage from occurring.

Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.

Abstract: Disclosed is a motor driving apparatus including: a motor; an inverter including a switching element for driving the motor; a controller for controlling the switching element; a resolver including an excitation winding and a detection winding; and a resolver chip applying an excitation signal to the excitation winding by inputting a periodic signal from the controller, and receiving a feedback signal from the detection winding, wherein the resolver chip determines the number of rotations of the motor based on a change in a pulse width of a detection signal resulting from a comparison between a voltage of the feedback signal and a preset voltage, and output a signal to the inverter for setting an inertial driving control mode according to the number of rotations of the motor in a failure state of the controller.

Abstract: A button type secondary battery includes a wound electrode assembly; a lower can with the electrode assembly and an electrolyte in the lower can; a top plate to close the lower can; a positive electrode terminal coupled to the top plate through a gasket to be electrically insulated from the top plate with a portion of the positive electrode terminal passing through a hole in the top plate to be bonded to a positive electrode tab; a top insulator covering a top surface of the electrode assembly; and a bottom insulator covering a bottom surface of the electrode assembly. The top insulator and the bottom insulator are each configured to expand in volume by absorbing the electrolyte. Surfaces of at least one or more of the top insulator and the bottom insulator are coated with a protective layer configured to prevent thermal shrinkage from occurring.

Abstract: A display that includes a display panel and a window laminated with the display panel is presented. The display panel may include: a main panel region including a first side extending in a first direction and a second side extending in a second direction crossing the first direction; a first sub-panel region that is in contact with the first side and is bent; and a second sub-panel region that is in contact with the second side and is bent. A panel corner part of the main panel region adjacent to the first sub-panel region and the second sub-panel region is rounded.

Abstract: Controlling a speed limit includes determining a virtual vehicle speed as being a lower one of a vehicle speed and a target limit speed, determining a virtual APS value as being a larger one of a first APS value and a second APS value, transitioning to a second mode at a point in time at which an actual APS value and the second APS value become different, when it is expected to transition to the second mode, among a first mode for sustaining a SOC of a battery at the target limit speed and the second mode for depleting the SOC, and determining a transmission gear position by applying the determined virtual vehicle speed and the determined virtual APS value to one of a first shifting pattern and a second shifting pattern.

Abstract: Disclosed is an apparatus for excitation signal generation for a resolver. The apparatus includes a sine wave generator that generates a sine wave based on a square wave, an amplifier that amplifies the sine wave, a differential signal generator that converts, into a differential signal, the amplified sine wave, a driver that inputs the differential signal to a coil, and a processor that generates an excitation signal by increasing a voltage of the sine wave from a start voltage to a target voltage through at least one of the sine wave generator and the amplifier based on a transient current that flows into the coil in a transient response interval.

Abstract: A brake lamp control method of a vehicle is provided. The method includes determining whether a deceleration of the vehicle based on regenerative brake through the electric motor is present in a hysteresis period between an off threshold as a reference for turning off a brake lamp and an on threshold as a reference for turning on the brake lamp. When the deceleration of the vehicle is present in the hysteresis period, the method includes determining a state of the brake lamp before the deceleration of the vehicle enters the hysteresis period. In response to determining that the brake lamp is turned on or off for a reason except for the regenerative brake before the deceleration of the vehicle enters the hysteresis period, a request for turning on the brake lamp is set or reset based on the regenerative brake in response to the determined state of the brake lamp.

Abstract: A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.

Abstract: A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.

Abstract: A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.

Abstract: A data training device includes a training control block configured to activate driving signals for driving a bit line sense amplifier, with a word line deactivated, when a write training operation is performed according to a mode register write command; and the bit line sense amplifier configured to store training data according to the driving signals from the training control block.

Abstract: A data training device includes a training control block configured to activate driving signals for driving a bit line sense amplifier, with a word line deactivated, when a write training operation is performed according to a mode register write command; and the bit line sense amplifier configured to store training data according to the driving signals from the training control block.

Abstract: A semiconductor device includes a plurality of oscillation signal generation units configured to output a plurality of oscillation signals whose cycles are adjusted according to a PN ratio, which is a size ratio of a PMOS transistor to an NMOS transistor, and a selection unit configured to selectively output the oscillation signals outputted from the plurality of oscillation signal generation units in response to a test mode signal.

Abstract: A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.

Abstract: A setup/hold time control circuit includes a reference signal output unit that sets any one of multiple ports as a reference port and buffers a signal input through the reference port to output as a reference signal. The setup/hold time control circuit also includes a plurality of comparative signal output units that set the remaining ports as comparative ports. The comparative signal output unit synchronizes signals that are input from the comparative ports with the reference signal and outputs the signals as internal signals. The setup/hold time control circuit improves high speed operation of a semiconductor memory device by improving upon the setup/hold time difference between multiple ports.

Abstract: A semiconductor memory device includes a clock input unit configured to receive a first clock and a second clock from the external. The memory device further includes a frequency conversion unit configured to convert a frequency of the second clock so that the frequency of the second clock becomes identical to a frequency of the first clock, a phase comparison unit configured to compare a phase of the first clock with that of a clock outputted from the frequency conversion unit, and output a comparison signal corresponding to the comparison result, a logic level change unit configured to change a logic level of a training information signal when a logic level of the comparison signal is fixed for a given time after being changed, and a signal transfer unit configured to transfer the training information signal to the external.

Abstract: A semiconductor memory device includes a clock input unit configured to receive a first clock and a second clock from the external. The memory device further includes a frequency conversion unit configured to convert a frequency of the second clock so that the frequency of the second clock becomes identical to a frequency of the first clock, a phase comparison unit configured to compare a phase of the first clock with that of a clock outputted from the frequency conversion unit, and output a comparison signal corresponding to the comparison result, a logic level change unit configured to change a logic level of a training information signal when a logic level of the comparison signal is fixed for a given time after being changed, and a signal transfer unit configured to transfer the training information signal to the external.

Abstract: A setup/hold time control circuit includes a reference signal output unit that sets any one of multiple ports as a reference port and buffers a signal input through the reference port to output as a reference signal. The setup/hold time control circuit also includes a plurality of comparative signal output units that set the remaining ports as comparative ports. The comparative signal output unit synchronizes signals that are input from the comparative ports with the reference signal and outputs the signals as internal signals. The setup/hold time control circuit improves high speed operation of a semiconductor memory device by improving upon the setup/hold time difference between multiple ports.

Abstract: Disclosed is a buffer device for a clock enable signal in a memory device that is used when the memory device escapes from a self-refresh mode. The buffer device includes a first buffer for comparing a clock enable signal with an external reference voltage in accordance with a self-refresh flag signal, a second buffer for outputting a signal corresponding to the self-refresh flag signal as the clock enable signal, a comparator for comparing the external reference voltage applied from an outside with an internal reference voltage internally generated, and a switching unit for selecting and outputting an output of the first buffer if the external reference voltage is higher than the internal reference voltage and selecting and outputting an output of the second buffer if the external reference voltage is lower than the internal reference voltage in accordance with an output signal of the comparator.