Patents by Inventor Joo-Wan Lee

Joo-Wan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Surface treating method for cutting tools
    Patent number: 8404366
    Abstract: In a cutting tool, if the outermost ceramic coating layer is a ?-Al2O3 coating layer, then certain microns of the ?-Al2O3 layer will be transformed into an ?-Al2O3 by instantaneous melting, vaporization and solidification. Further, if the outermost coating layer of the ceramic coating layers is an ?-Al2O3 coating layer, then the surface roughness will be enhanced since at least a portion of it will be melted, wherein the melted surface will be solidified with its surface flattened by the surface tension provided in a melted state.
    Type: Grant
    Filed: January 2, 2007
    Date of Patent: March 26, 2013
    Assignee: TaeguTec, Ltd.
    Inventors: Dong Gil Ahn, Joo Wan Lee
  • Surface Treating Method for Cutting Tools
    Publication number: 20090317199
    Abstract: In a cutting tool, if the outermost ceramic coating layer is a ?-Al2O3 coating layer, then certain microns of the ?-Al2O3 layer will be transformed into an ?-Al2O3 by instantaneous melting, vaporization and solidification. Further, if the outermost coating layer of the ceramic coating layers is an ?-Al2O3 coating layer, then the surface roughness will be enhanced since at least a portion of it will be melted, wherein the melted surface will be solidified with its surface flattened by the surface tension provided in a melted state.
    Type: Application
    Filed: January 2, 2007
    Publication date: December 24, 2009
    Applicant: Taegu Tec , Ltd.
    Inventors: Dong Gil Ahn, Joo Wan Lee
  • Method for fabricating semiconductor device
    Patent number: 7338871
    Abstract: The present invention provides a method for fabricating a semiconductor device capable of preventing a contact resistance from increasing in a region contacted to an N-type conductive region during forming a conductive pattern directly contacted to the N-type conductive region including a conductive pattern and silicon, and preventing an increase in a parasitic capacity of the conductive pattern according to an increase in a thickness of a barrier layer.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: March 4, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Joo-Wan Lee, Jun-Ki Kim
  • Method for fabricating semiconductor device
    Publication number: 20050287799
    Abstract: The present invention provides a method for fabricating a semiconductor device capable of preventing a contact resistance from increasing in a region contacted to an N-type conductive region during forming a conductive pattern directly contacted to the N-type conductive region including a conductive pattern and silicon, and preventing an increase in a parasitic capacity of the conductive pattern according to an increase in a thickness of a barrier layer.
    Type: Application
    Filed: December 21, 2004
    Publication date: December 29, 2005
    Inventors: Joo-Wan Lee, Jun-Ki Kim