Patents by Inventor Joo-won Lee

Joo-won Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080280391
    Abstract: In some methods of manufacturing transistors, a gate electrode and a gate insulation layer pattern are stacked on a substrate. Impurity regions are formed at portions of the substrate that are adjacent to the gate electrode by implanting Group III impurities into the portions of the substrate. A diffusion preventing layer is formed on the substrate and covering the gate electrode. A nitride layer is formed on the diffusion preventing layer. The substrate is thermally treated to form a strained silicon region in the substrate between the impurity regions and to activate the impurities in the impurity regions. A high performance PMOS transistor and/or CMOS transistor may thereby be manufactured on the substrate.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 13, 2008
    Inventors: Dong-Suk Shin, Joo-Won Lee, Tae-Gyun Kim
  • Patent number: 7391152
    Abstract: The present invention discloses an inorganic thin layer which is composed of an inorganic composite containing at least two kinds of inorganic materials and shows excellent moisture and oxygen proof, an organic electroluminescence device including the inorganic thin layer as a passivation layer, and a fabrication method thereof.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: June 24, 2008
    Assignee: Korea Institute of Science and Technology
    Inventors: Byeong-Kwon Ju, Jai-Kyeong Kim, Young-Chul Kim, Hoon Kim, Kwang-Ho Kim, Joo-Won Lee
  • Publication number: 20070166885
    Abstract: In an electrode line structure of a semiconductor device and a method for forming the same, the electrode line structure comprises a semiconductor substrate, and electrode lines, which are formed on the semiconductor substrate, and have an inclined end in the long axis direction. The electrode lines each include a first line unit, which substantially functions as an electrode line, a second line unit, which has an inclined end in the long axis direction and is separated from the first line unit by a predetermined distance, and an insulating plug, which is interposed between the first line unit and the second line unit and electrically insulates the first line unit from the second line unit.
    Type: Application
    Filed: January 9, 2007
    Publication date: July 19, 2007
    Inventors: Joo-won Lee, Kang-soo Chu, Jae-eun Park, Jong-ho Yang
  • Patent number: 7180190
    Abstract: In an electrode line structure of a semiconductor device and a method for forming the same, the electrode line structure comprises a semiconductor substrate, and electrode lines, which are formed on the semiconductor substrate, and have an inclined end in the long axis direction. The electrode lines each include a first line unit, which substantially functions as an electrode line, a second line unit, which has an inclined end in the long axis direction and is separated from the first line unit by a predetermined distance, and an insulating plug, which is interposed between the first line unit and the second line unit and electrically insulates the first line unit from the second line unit.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: February 20, 2007
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Joo-won Lee, Kang-soo Chu, Jae-eun Park, Jong-ho Yang
  • Patent number: 7084076
    Abstract: A method is provided for forming a silicon dioxide film using atomic layer deposition (ALD), wherein a halogen- or NCO-substituted siloxane is used as a Si source. The method includes feeding a substituted siloxane as a first reactant onto a substrate to form a chemisorbed layer of the first reactant, and thereafter feeding a compound consisting of oxygen and hydrogen as a second reactant onto the chemisorbed layer to form the desired silicon dioxide film.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: August 1, 2006
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Jae-eun Park, Kang-soo Chu, Joo-won Lee, Jong-ho Yang
  • Publication number: 20060040510
    Abstract: Improved methods are disclosed for catalyst-assisted atomic layer deposition (ALD) to form a silicon dioxide layer having superior properties on a semiconductor substrate by using a first reactant component consisting of a silicon compound having at least two silicon atoms, or using a tertiary aliphatic amine as the catalyst component, or both in combination, together with related purging methods and sequencing.
    Type: Application
    Filed: September 14, 2005
    Publication date: February 23, 2006
    Inventors: Joo-won Lee, Jae-eun Park, Jong-ho Yang, Kang-soo Chu
  • Patent number: 6992019
    Abstract: Improved methods are disclosed for catalyst-assisted atomic layer deposition (ALD) to form a silicon dioxide layer having superior properties on a semiconductor substrate by using a first reactant component consisting of a silicon compound having at least two silicon atoms, or using a tertiary aliphatic amine as the catalyst component, or both in combination, together with related purging methods and sequencing.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: January 31, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-won Lee, Jae-eun Park, Jong-ho Yang, Kang-soo Chu
  • Patent number: 6989231
    Abstract: Provided is a method of forming a fine pattern, in which a silicon oxide layer is formed on a photoresist pattern and dry etching is performed on the resultant structure. According to the method, a photoresist pattern is formed on a material layer on which a fine pattern is to be formed, a silicon oxide layer is conformally deposited on the photoresist pattern without damaging the photoresist pattern, and dry etching is performed on a lower layer. During the dry etching, spacers are formed along the sidewalls of the photoresist pattern, and then, a polymer layer is formed on the photoresist pattern. Accordingly, it is possible to prevent the thinning of the photoresist pattern so that a desired pattern can be obtained, and further, to prevent striation or wiggling from occurring on the patterned material layer.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: January 24, 2006
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Jae-eun Park, Kang-soo Chu, Joo-won Lee, Jong-ho Yang
  • Publication number: 20050146037
    Abstract: Provided are a semiconductor device having an etch stopper formed of a nitride film by low temperature atomic layer deposition which can prevent damage to a semiconductor substrate and a method for fabricating the semiconductor device. Damage to the semiconductor substrate under the etch stopper composed of a second nitride film can be prevented by forming a first nitride film using high temperature LPCVD on the semiconductor substrate, forming the etch stopper including the second nitride film by low temperature ALD on the first nitride film, and removing the second nitride film by dry etching, thus taking advantage of the different etch selectivities of the first nitride film and the second nitride film.
    Type: Application
    Filed: December 29, 2004
    Publication date: July 7, 2005
    Inventors: Kang-soo Chu, Joo-won Lee, Jae-eun Park, Jong-ho Yang
  • Publication number: 20050142781
    Abstract: Provided are a semiconductor device having an etch stopper formed of a nitride film by low temperature atomic layer deposition which can prevent damage to a semiconductor substrate and a method for fabricating the semiconductor device. Damage to the semiconductor substrate under the etch stopper composed of a second nitride film can be prevented by forming a first nitride film using high temperature LPCVD on the semiconductor substrate, forming the etch stopper including the second nitride film by low temperature ALD on the first nitride film, and removing the second nitride film by dry etching, thus taking advantage of the different etch selectivities of the first nitride film and the second nitride film.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 30, 2005
    Inventors: Kang-soo Chu, Joo-won Lee, Jae-eun Park, Jong-ho Yang
  • Publication number: 20050046339
    Abstract: The present invention discloses an inorganic thin layer which is composed of an inorganic composite containing at least two kinds of inorganic materials and shows excellent moisture and oxygen proof, an organic electroluminescence device including the inorganic thin layer as a passivation layer, and a fabrication method thereof.
    Type: Application
    Filed: August 23, 2004
    Publication date: March 3, 2005
    Inventors: Byeong-Kwon Ju, Jai-Kyeong Kim, Young-Chul Kim, Hoon Kim, Kwang-Ho Kim, Joo-Won Lee
  • Publication number: 20040180557
    Abstract: A method is provided for forming a silicon dioxide film using atomic layer deposition (ALD), wherein a halogen- or NCO-substituted siloxane is used as a Si source. The method includes feeding a substituted siloxane as a first reactant onto a substrate to form a chemisorbed layer of the first reactant, and thereafter feeding a compound consisting of oxygen and hydrogen as a second reactant onto the chemisorbed layer to form the desired silicon dioxide film.
    Type: Application
    Filed: February 19, 2004
    Publication date: September 16, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-eun Park, Kang-soo Chu, Joo-won Lee, Jong-ho Yang
  • Publication number: 20040180483
    Abstract: Provided is a method of manufacturing a semiconductor device with an LDD structure using a decreased number of mask-patterning processes using photolithography. The method includes forming an LDD region by implanting low-concentration impurity ions into a semiconductor substrate using a gate electrode, the sidewall of which are exposed, as an ion implantation mask. Then, to form a source/drain region, high-concentration impurity ions are implanted into the semiconductor substrate using a sacrificial masking layer, which covers the top surface and sidewalls of the gate electrode and the top surface of the semiconductor substrate to a uniform thickness, as an ion implantation mask. Implantation of the high-concentration impurity ions may be performed before or after implantation of the low-concentration impurity ions. When a CMOS transistor is formed, additional masks to be used as ion implantation masks are not required for implanting high-concentration impurity ions to form source/drain regions.
    Type: Application
    Filed: March 8, 2004
    Publication date: September 16, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-eun Park, Kang-soo Chu, Joo-won Lee, Jong-ho Yang
  • Publication number: 20040166627
    Abstract: Methods of forming a capacitor on an integrated circuit include forming a lower electrode of the capacitor on an integrated circuit substrate. A protection layer is formed on the lower electrode at a temperature below a minimum temperature associated with a phase change of the lower electrode. A dielectric layer is formed on the protection layer. The protection layer is configured to limit oxidation of the lower electrode during forming of the dielectric layer. An upper electrode of the capacitor is formed on the dielectric layer.
    Type: Application
    Filed: July 29, 2003
    Publication date: August 26, 2004
    Inventors: Jae-Soon Lim, Sung-Tae Kim, Young-Sun Kim, Ki-Hyun Hwang, Gab-Jin Nam, Ki-Chul Kim, Joo-Won Lee, Jae-Young Park
  • Publication number: 20040107897
    Abstract: Provided is an atomic layer deposition (ALD) apparatus in which the generation of powders is suppressed by providing a largely dedicated exhaust path for each of the reactants utilized in the ALD process. The ALD apparatus includes a reactor in which an ALD process is performed on a wafer using two or more types of reactants; reactant suppliers, each of which alternately supplies a different reactant to the reactor; and an exhaust path for each type of reactant so that the non-reacted portion of the reactants removed from the reaction chamber do not mix and react in the exhaust path.
    Type: Application
    Filed: August 14, 2003
    Publication date: June 10, 2004
    Inventors: Seung-Hwan Lee, Kang-Soo Chu, Joo-Won Lee, Jae-Eun Park, Jong-Ho Yang
  • Publication number: 20040056292
    Abstract: In an electrode line structure of a semiconductor device and a method for forming the same, the electrode line structure comprises a semiconductor substrate, and electrode lines, which are formed on the semiconductor substrate, and have an inclined end in the long axis direction. The electrode lines each include a first line unit, which substantially functions as an electrode line, a second line unit, which has an inclined end in the long axis direction and is separated from the first line unit by a predetermined distance, and an insulating plug, which is interposed between the first line unit and the second line unit and electrically insulates the first line unit from the second line unit.
    Type: Application
    Filed: July 2, 2003
    Publication date: March 25, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Joo-Won Lee, Kang-Soo Chu, Jae-Eun Park, Jong-Ho Yang
  • Publication number: 20040046189
    Abstract: Provided are a semiconductor device having an etch stopper formed of a nitride film by low temperature atomic layer deposition which can prevent damage to a semiconductor substrate and a method for fabricating the semiconductor device. Damage to the semiconductor substrate under the etch stopper composed of a second nitride film can be prevented by forming a first nitride film using high temperature LPCVD on the semiconductor substrate, forming the etch stopper including the second nitride film by low temperature ALD on the first nitride film, and removing the second nitride film by dry etching, thus taking advantage of the different etch selectivities of the first nitride film and the second nitride film.
    Type: Application
    Filed: July 2, 2003
    Publication date: March 11, 2004
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Kang-Soo Chu, Joo-Won Lee, Jae-Eun Park, Jong-Ho Yang
  • Patent number: 6699689
    Abstract: The present invention relates to DNA constructs that can produce antimicrobial materials efficiently from microorganisms and the preparation method thereof. The present invention also relates to the useful vector for the DNA construct. The DNA construct according to the present invention comprises a first gene coding for entire, a part of or a derivative of purF gene and a second gene coding for antimicrobial peptide. According to the present invention, antimicrobial peptides can be mass-produced by the following steps: preparing an expression vector containing a DNA construct comprising a first gene coding for an entire, a part of or a derivative of purF gene and a second gene coding for antimicrobial peptide; transforming the bacterial host cells with the above-mentioned vector, culturing the transformed cell to express the above-mentioned DNA construct; and recovering the above antimicrobial peptide.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: March 2, 2004
    Assignee: Samyang Genex Corporation
    Inventors: Jeong Hyun Kim, Min Hyung Kang, Jae Hyun Lee, Se Ho Park, Joo Won Lee, Seung Suh Hong, Hyun Soo Lee
  • Publication number: 20040029052
    Abstract: Provided is a method of forming a fine pattern, in which a silicon oxide layer is formed on a photoresist pattern and dry etching is performed on the resultant structure. According to the method, a photoresist pattern is formed on a material layer on which a fine pattern is to be formed, a silicon oxide layer is conformally deposited on the photoresist pattern without damaging the photoresist pattern, and dry etching is performed on a lower layer. During the dry etching, spacers are formed along the sidewalls of the photoresist pattern, and then, a polymer layer is formed on the photoresist pattern. Accordingly, it is possible to prevent the thinning of the photoresist pattern so that a desired pattern can be obtained, and further, to prevent striation or wiggling from occurring on the patterned material layer.
    Type: Application
    Filed: June 3, 2003
    Publication date: February 12, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-eun Park, Kang-soo Chu, Joo-won Lee, Jong-ho Yang
  • Patent number: 6689696
    Abstract: A method for manufacturing a semiconductor device employing a dielectric layer for forming a conductive layer into a three-dimensional shape. The dielectric layer is formed on a substrate in such a manner as to provide an intrinsic etch rate within the layer which increases in the direction of the thickness or depth of the dielectric layer. This variable intrinsic etch rate within the dielectric layer is achieved by changing one of a plurality of deposition variables. Once formed, the dielectric layer is selectively etched to form a through hole to contact a conductive area underlying the dielectric layer. A conductive layer is formed in the through hole, which may be a storage node of a capacitor.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: February 10, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-won Lee, Ki-yeon Park