Patents by Inventor Joo-Yong Park
Joo-Yong Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957141Abstract: An apparatus and method for manufacturing a grilled seaweed includes the apparatus comprising a grilling unit having a first housing with a first inlet opening and a first outlet opening which communicate with each other; a first conveyor for transferring a sheet of seaweed from the first inlet opening to the first outlet opening; a first heating source installed over the first conveyor to discharge a flame onto a top surface of the seaweed being transferred by the first conveyor; and a second heating source installed on both sides of a lower portion of the first conveyor to apply a flame onto a bottom surface of the seaweed being transferred by the first conveyor.Type: GrantFiled: July 18, 2017Date of Patent: April 16, 2024Assignees: CJ CHEILJEDANG CORPORATION, CJ SEAFOOD CORPORATIONInventors: Joo Dong Park, Chang Yong Lee, Eun Soo Kwak, Dae Ik Kang, Tae Hyeong Kim, Young Sub Choi
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Patent number: 11961564Abstract: To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.Type: GrantFiled: October 18, 2021Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-Yeon Yu, Kui-Han Ko, Il-Han Park, June-Hong Park, Joo-Yong Park, Joon-Young Park, Bong-Soon Lim
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Patent number: 11922543Abstract: A method, performed by a coloring apparatus, of coloring a sketch image includes adding a color pointer on the sketch image, according to an input of a user; determining an object related to a point where the color pointer is located, from among objects configuring the sketch image; and generating a colored image by coloring the determined object, based on a color of the color pointer.Type: GrantFiled: January 18, 2022Date of Patent: March 5, 2024Assignee: NAVER WEBTOON LTD.Inventors: Jun Hyun Park, Yu Ra Shin, Du Yong Lee, Joo Young Moon
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Patent number: 11913773Abstract: The present invention relates to a method of non-destructively measuring a thickness of a reinforcement membrane, and more particularly, to a method of non-destructively measuring a thickness of a hydrogen ion exchange reinforcement membrane for a fuel cell, in which the reinforcement membrane has a symmetric three-layer structure including a reinforcement base layer and pure water layers disposed at opposing sides of the reinforcement base layer, including performing total non-destructive inspection and omitting a process of analyzing a position by means of a thickness peak of a power spectrum of the respective layers of the reinforcement membrane.Type: GrantFiled: May 20, 2019Date of Patent: February 27, 2024Assignee: LG CHEM, LTD.Inventors: Sung-Hyun Yun, Joo-Yong Park, Ji-Hun Kim, Jae-Choon Yang
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Patent number: 11866279Abstract: The present invention relates to a film wrinkle removing roller in which pattern rolls coated with rubber are positioned at both ends of a cylindrical roll made of Teflon, and a porous film comes into contact with the roll and the pattern rolls, such that the film may be prevented from wrinkling and a surface of the film may be prevented from being abraded due to friction between the film and surfaces of the rolls.Type: GrantFiled: May 2, 2019Date of Patent: January 9, 2024Assignee: LG CHEM, LTD.Inventors: Sung Hyun Yun, Ji Hun Kim, Joo Yong Park, Jae Choon Yang
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Publication number: 20230175943Abstract: According to a system and method for evaluating the dissolution quality of a binder solution for a secondary battery electrode, by preparing an electrode slurry with a binder solution having a predetermined amount or more of cumulative filtration amount or a predetermined level or less of flow rate reduction rate, the quality of an electrode for a secondary battery may be improved.Type: ApplicationFiled: March 21, 2022Publication date: June 8, 2023Applicant: LG ENERGY SOLUTION, LTD.Inventors: Young Seok KIM, Joo Yong PARK, Sung Soo YOON, Je Gwon LEE, Hye Jin SIM, Hyeon Jeong KANG
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Patent number: 11664361Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.Type: GrantFiled: January 18, 2022Date of Patent: May 30, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chanho Kim, Joo-Yong Park, Daeseok Byeon
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Publication number: 20230065440Abstract: A method for managing an application executed in a user terminal according to an embodiment of this disclosure includes executing a launcher application on the user terminal, displaying a first application list within a first GUI of the launcher application, installing, in the user terminal, a first application selected by a user from applications included on the first application list, displaying a second application list within a second GUI of the launcher application and executing a second application selected by the user from applications included on the second application list.Type: ApplicationFiled: July 20, 2022Publication date: March 2, 2023Inventors: Jae Chun OH, A Reum HAN, Sung Pyo LEE, Hye Mi SEO, Hye Jung JUNG, Go Eun LEE, Da In UM, Jung Jun LEE, Ah Ra KO, Joo Yong PARK, Hee Suk JEONG
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Patent number: 11489173Abstract: The present invention relates to a fuel cell and a fuel cell stack comprising the same, and according to one aspect of the present invention, there is provided a fuel cell comprising a membrane-electrode assembly having a first surface and a second surface opposite to the first surface, wherein an anode electrode and a cathode electrode are each disposed on the first surface; an end plate disposed apart at a predetermined interval on the second surface; a first gas diffusion layer disposed on the anode electrode; a second gas diffusion layer disposed on the cathode electrode; a first separating plate disposed on the first gas diffusion layer and having a plurality of flow channels; and a second separating plate disposed on the second gas diffusion layer and having a plurality of flow channels.Type: GrantFiled: January 31, 2019Date of Patent: November 1, 2022Assignee: LG CHEM, LTD.Inventors: Sung Hyun Yun, Joo Yong Park, Do Young Kim, Woon Jo Kim, Kyung Mun Kang, Jae Choon Yang
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Publication number: 20220317010Abstract: A system for determining a filter for evaluating a dissolution quality of a binder solution for a secondary battery electrode according to the present technology includes: a pressure container which accommodates a binder solution; a pressure medium supply source which supplies pressure medium of a predetermined pressure to the pressure container; a filter which is connected to the pressure container by a pipe; a flow rate measuring unit which measures a flow rate of the binder solution filtered by the filter; and a determination unit which measures a time point when a flow rate reaches a specific value predetermined in consideration of an initial flow rate by repeating measurement of the flow rate using each filter having a different pore size, and determines a filter having a filter size in an optimal pore size range based on the time point.Type: ApplicationFiled: February 2, 2022Publication date: October 6, 2022Applicant: LG ENERGY SOLUTION, LTD.Inventors: Hye Jin SIM, Joo Yong PARK, Sung Soo YOON, Je Gwon LEE, Hyeon Jeong KANG, Young Seok KIM
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Publication number: 20220139897Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.Type: ApplicationFiled: January 18, 2022Publication date: May 5, 2022Inventors: CHANHO KIM, JOO-YONG PARK, DAESEOK BYEON
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Publication number: 20220036954Abstract: To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.Type: ApplicationFiled: October 18, 2021Publication date: February 3, 2022Inventors: Chang-Yeon YU, Kui-Han KO, Il-Han PARK, June-Hong PARK, Joo-Yong PARK, Joon-Young PARK, Bong-Soon LIM
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Patent number: 11233042Abstract: A three-dimensional semiconductor memory device, including a first chip and a second chip stacked on the first chip may be provided. The first chip may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, and second contact plugs, and a passive device on and electrically connected to the second contact plugs. The second chip may include a second substrate including a cell array region and a contact region, which vertically overlap the second peripheral circuit region and the first peripheral circuit region of the first chip, respectively. The second chip may further include gate electrodes, and cell contact plugs disposed on the contact region of the second substrate and on end portions of the gate electrodes. The first passive device may be vertically between the gate electrodes and the second contact plugs and may include a first contact line.Type: GrantFiled: April 16, 2020Date of Patent: January 25, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chanho Kim, Joo-Yong Park, Daeseok Byeon
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Patent number: 11233043Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.Type: GrantFiled: August 25, 2020Date of Patent: January 25, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chanho Kim, Joo-Yong Park, Daeseok Byeon
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Patent number: 11183249Abstract: To program in a nonvolatile memory device, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.Type: GrantFiled: September 25, 2018Date of Patent: November 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-Yeon Yu, Kui-Han Ko, Il-Han Park, June-Hong Park, Joo-Yong Park, Joon-Young Park, Bong-Soon Lim
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Publication number: 20210207946Abstract: The present invention relates to a method of non-destructively measuring a thickness of a reinforcement membrane, and more particularly, to a method of non-destructively measuring a thickness of a hydrogen ion exchange reinforcement membrane for a fuel cell, in which the reinforcement membrane has a symmetric three-layer structure including a reinforcement base layer and pure water layers disposed at opposing sides of the reinforcement base layer, including performing total non-destructive inspection and omitting a process of analyzing a position by means of a thickness peak of a power spectrum of the respective layers of the reinforcement membrane.Type: ApplicationFiled: May 20, 2019Publication date: July 8, 2021Applicant: LG CHEM, LTD.Inventors: Sung-Hyun YUN, Joo-Yong PARK, Ji-Hun KIM, Jae-Choon YANG
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Publication number: 20210198071Abstract: The present invention relates to a film wrinkle removing roller in which pattern rolls coated with rubber are positioned at both ends of a cylindrical roll made of Teflon, and a porous film comes into contact with the roll and the pattern rolls, such that the film may be prevented from wrinkling and a surface of the film may be prevented from being abraded due to friction between the film and surfaces of the rolls.Type: ApplicationFiled: May 2, 2019Publication date: July 1, 2021Applicant: LG CHEM, LTD.Inventors: Sung Hyun YUN, Ji Hun KIM, Joo Yong PARK, Jae Choon YANG
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Publication number: 20210083302Abstract: The present invention relates to a fuel cell and a fuel cell stack comprising the same, and according to one aspect of the present invention, there is provided a fuel cell comprising a membrane-electrode assembly having a first surface and a second surface opposite to the first surface, wherein an anode electrode and a cathode electrode are each disposed on the first surface; an end plate disposed apart at a predetermined interval on the second surface; a first gas diffusion layer disposed on the anode electrode; a second gas diffusion layer disposed on the cathode electrode; a first separating plate disposed on the first gas diffusion layer and having a plurality of flow channels; and a second separating plate disposed on the second gas diffusion layer and having a plurality of flow channels.Type: ApplicationFiled: January 31, 2019Publication date: March 18, 2021Inventors: Sung Hyun YUN, Joo Yong PARK, Do Young KIM, Woon Jo KIM, Kyung Mun KANG, Jae Choon YANG
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Publication number: 20210066277Abstract: A three-dimensional semiconductor memory device, including a first chip and a second chip stacked on the first chip may be provided. The first chip may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, and second contact plugs, and a passive device on and electrically connected to the second contact plugs. The second chip may include a second substrate including a cell array region and a contact region, which vertically overlap the second peripheral circuit region and the first peripheral circuit region of the first chip, respectively. The second chip may further include gate electrodes, and cell contact plugs disposed on the contact region of the second substrate and on end portions of the gate electrodes. The first passive device may be vertically between the gate electrodes and the second contact plugs and may include a first contact line.Type: ApplicationFiled: April 16, 2020Publication date: March 4, 2021Inventors: CHANHO KIM, JOO-YONG PARK, DAESEOK BYEON
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Publication number: 20210066282Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.Type: ApplicationFiled: August 25, 2020Publication date: March 4, 2021Inventors: CHANHO KIM, JOO-YONG PARK, DAESEOK BYEON