Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.

Abstract: Embodiments herein relate to systems, apparatuses, or processes for a connector for a modular memory package that includes one or more memory dies on a substrate, where the connector directly electrically couples electrical contacts at an edge and on each side the substrate of the memory package to electrical contacts at an edge and on each side of another substrate that includes a compute die. The connector may include a first plurality of leads that are substantially parallel with each other, and a second plurality of leads that are substantially parallel with each other that are below the first plurality of leads and electrically couple the two substrates. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes for stiffeners for a surface of a package substrate, where the stiffeners provide EMI/RFI shielding for signal traces or other electrical routings within the package, and in particular for traces at a surface of the package such as microstrip routings. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for packages that include a die complex with a base die that is coupled with a HDP substrate that in turn is coupled with an mSAP board. The HDP substrate may have a small trace width and trace spacing, for example three ?m or less, that enable the HDP substrate to be used as a pitch translator between the base die and the mSAP board, for example between a 110 ?m pitch and a 210 ?m pitch. One or more DRAM modules may be coupled with the mSAP board. The configuration has a reduced overall package height. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a stiffener for a surface of a semiconductor package, where the stiffener includes slots that allow a gasket to go over the stiffener to electrically couple with a ground or a VSS of the semiconductor package. In embodiments, the gasket may include a material that blocks or absorbs EMI or RFI. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a die. In an embodiment, a package substrate is coupled to the die. In an embodiment, a ring is provided under the package substrate. In an embodiment, the ring comprises a conductive material. In an embodiment, the electronic package further comprises balls outside of the ring.

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes directed to an electrical conductor, or power corridor, on the outside of a package substrate, wherein the electrical conductor is raised, or extends from a surface of the package substrate. In embodiments, this electrical conductor may be used to reduce the number of layers required within the package substrate by removing power planes within the substrate to the electrical conductors on the surface of the package. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a base coupled to the package substrate. In an embodiment, a die is coupled to the base, and a memory die module is over the die.

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a cutout. In an embodiment, pads are adjacent to the cutout. In an embodiment, a memory die stack is on the package substrate, where the memory die stack is electrically coupled to the pads by routing in the package substrate. In an embodiment, a die is over the cutout, where the die is supported by the pads.

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core. In an embodiment, the core comprises a first sub-core layer and a second sub-core layer. In an embodiment, a via is provided through the first sub-core layer and the second sub-core layer. In an embodiment, the via comprises a first hourglass shape in the first sub-core layer and a second hourglass shape in the second sub-core layer. In an embodiment, a front-side buildup layer is over the core and a backside buildup layer is under the core.

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, a package substrate comprises a core, a first layer on the core, where the first layer comprises a first plane, a second layer on the first layer, where the second layer comprises first traces and second traces arranged in an alternating pattern, a third layer on the second layer, where the third layer comprises third traces and fourth traces arranged in an alternating pattern, and a fourth layer over the third layer, where the fourth layer comprises a second plane.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate with a first memory die stack on the package substrate, and a second memory die stack on the package substrate. In an embodiment, an electrically insulating layer is provided over the first memory die stack and the second memory die stack. In an embodiment, an opening is provided through the electrically insulating layer, and a die module is in the opening over the package substrate.