Patents by Inventor Joon Gon Lee
Joon Gon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126074Abstract: The present disclosure provides a waveguide display apparatus. The waveguide waveguide display apparatus of the present disclosure is a waveguide display apparatus for correcting curved surface reflection distortion, the waveguide display apparatus including a waveguide for guiding light inputted from the outside; a first diffractive optical element disposed at the waveguide, and diffracting the light inputted from the outside to the inside of the waveguide; and a second diffractive optical element disposed at the waveguide, and diffracting the light guided by the waveguide to output a plurality of diffracted lights in a direction of a curved surface reflector located outside, wherein the second diffractive optical element has a structure of a diffraction grating corresponding to a curvature of the curved surface reflector such that the diffracted lights are reflected at different locations of the curved surface reflector in directions parallel to each other.Type: ApplicationFiled: September 30, 2022Publication date: April 18, 2024Applicant: LG Chem, Ltd.Inventors: Jae Jin Kim, Bo Ra Jung, Hye Won Hwang, Yeon Jae Yoo, Joon Young Lee, Bu Gon Shin, Min Soo Song
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Publication number: 20220319916Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.Type: ApplicationFiled: June 13, 2022Publication date: October 6, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won Keun CHUNG, Joon Gon LEE, Rak Hwan KIM, Chung Hwan SHIN, Do Sun LEE, Nam Gyu CHO
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Patent number: 11367651Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.Type: GrantFiled: June 16, 2020Date of Patent: June 21, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won Keun Chung, Joon Gon Lee, Rak Hwan Kim, Chung Hwan Shin, Do Sun Lee, Nam Gyu Cho
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Publication number: 20210020500Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.Type: ApplicationFiled: June 16, 2020Publication date: January 21, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won Keun Chung, Joon Gon Lee, Rak Hwan Kim, Chung Hwan Shin, Do Sun Lee, Nam Gyu Cho
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Patent number: 10332984Abstract: A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an upper surface in which a recessed region is formed, a contact plug on the source/drain regions and extending in a direction substantially perpendicular to an upper surface of the substrate from an interior of the recessed region, a metal silicide film on an internal surface of the recessed region and including a first portion between a bottom surface of the recessed region and a lower surface of the contact plug and a second portion between a side wall of the recessed region and a side surface of the contact plug, and a metal layer connected to an upper portion of the metal silicide film and on a side surface of a region of the contact plug.Type: GrantFiled: March 29, 2017Date of Patent: June 25, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo Seok Choi, Ryuji Tomita, Joon Gon Lee, Chul Sung Kim, Jae Eun Lee
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Patent number: 10283600Abstract: An integrated circuit device includes a substrate, a gate structure, a spacer structure, a source/drain region, and a first contact structure. The substrate includes a fin-type active region. The gate structure intersects with the fin-type active region on the substrate, and has two sides and two side walls. The spacer structure is disposed on both side walls of the gate structure and includes a first spacer layer contacting at least a portion of both side walls of the gate structure and a second spacer layer disposed on the first spacer layer and having a lower dielectric constant than a dielectric constant of the first spacer layer. The source/drain region is disposed on both sides of the gate structure. The first contact structure is electrically connected to the source/drain region and includes a first contact plug disposed on the source/drain region and a first metallic capping layer disposed on the first contact plug.Type: GrantFiled: January 15, 2018Date of Patent: May 7, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Gon Lee, Ryuji Tomita, Chul-Sung Kim, Sang-Jin Hyun
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Publication number: 20190115451Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming an active pattern on a substrate, forming a gate electrode traversing the active pattern on the active pattern, forming a recess adjacent to a sidewall of the gate electrode in the active pattern, and performing a chemical vapor deposition process using a source gas and a doping gas to form a source/drain region in the recess. The source gas may include a silicon precursor and a germanium precursor, and the doping gas may include a gallium precursor and a boron precursor.Type: ApplicationFiled: August 1, 2018Publication date: April 18, 2019Inventors: Joon Gon Lee, Kuo Tai Huang, Ryuji Tomita
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Patent number: 10262937Abstract: An integrated circuit device includes at least one fin-type active region, a gate line on the at least one fin-type active region, and a source/drain region on the at least one fin-type active region at at least one side of the gate line. A first conductive plug is connected to the source/drain region and includes cobalt. A second conductive plug is connected to the gate line and spaced apart from the first conductive plug. A third conductive plug is connected to each of the first conductive plug and the second conductive plug. The third conductive plug electrically connects the first conductive plug and the second conductive plug.Type: GrantFiled: August 17, 2017Date of Patent: April 16, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-gon Lee, Ryuji Tomita, Do-Sun Lee, Chul-sung Kim, Do-hyun Lee
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Publication number: 20190043959Abstract: An integrated circuit device includes a substrate, a gate structure, a spacer structure, a source/drain region, and a first contact structure. The substrate includes a fin-type active region. The gate structure intersects with the fin-type active region on the substrate, and has two sides and two side walls. The spacer structure is disposed on both side walls of the gate structure and includes a first spacer layer contacting at least a portion of both side walls of the gate structure and a second spacer layer disposed on the first spacer layer and having a lower dielectric constant than a dielectric constant of the first spacer layer. The source/drain region is disposed on both sides of the gate structure. The first contact structure is electrically connected to the source/drain region and includes a first contact plug disposed on the source/drain region and a first metallic capping layer disposed on the first contact plug.Type: ApplicationFiled: January 15, 2018Publication date: February 7, 2019Inventors: Joon-Gon Lee, Ryuji Tomita, Chul-Sung Kim, Sang-Jin Hyun
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Patent number: 10128245Abstract: Semiconductor devices may have a first semiconductor element including first active regions that are doped with a first conductivity-type impurity and that are on a semiconductor substrate, a first gate structure between the first active regions, and first contacts connected to the first active regions, respectively; and a second semiconductor element including second active regions that are doped with a second conductivity-type impurity different from the first conductivity-type impurity and that are on the semiconductor substrate, a second gate structure between the second active regions, and second contacts connected to the second active regions, respectively, and having a second length greater than a first length of each of the first contacts in a first direction parallel to an upper surface of the semiconductor substrate.Type: GrantFiled: March 29, 2017Date of Patent: November 13, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Do Sun Lee, Joon Gon Lee, Na Rae Kim, Chul Sung Kim, Do Hyun Lee, Ryuji Tomita, Sang Jin Hyun
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Patent number: 10115806Abstract: A semiconductor device includes a substrate with lower structures, an insulation layer covering the lower structures on the substrate, a contact hole through the insulation layer partially exposing the substrate, and a contact structure contacting the substrate through the contact hole, the contact structure including a barrier pattern having an upper barrier on an upper portion of a sidewall of the contact hole, and a lower barrier filling a lower portion of the contact hole, and a conductive contact pattern filling an upper portion of the contact hole defined by the upper barrier and the lower barrier.Type: GrantFiled: May 26, 2016Date of Patent: October 30, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-Hwa Kim, Joon-Gon Lee, Inchan Hwang
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Patent number: 10079210Abstract: An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction, a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction, a conductive region on a portion of the at least one fin-shaped active region at one side of the gate line, and a contact plug extending from the conductive region in a third direction, the third direction being perpendicular to a main plane of the substrate, may be provided. The contact plug may include a metal plug, a conductive barrier film on the conductive region, the conductive barrier film surrounding a sidewall and a bottom surface of the metal plug, the conductive barrier film including an N-rich metal nitride film, and a metal silicide film between the conductive region and the conductive barrier film.Type: GrantFiled: June 20, 2016Date of Patent: September 18, 2018Assignee: Samsung Electroics Co., Ltd.Inventors: Do-sun Lee, Do-hyun Lee, Chul-sung Kim, Sang-jin Hyun, Joon-gon Lee
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Publication number: 20180261540Abstract: An integrated circuit device includes at least one fin-type active region, a gate line on the at least one fin-type active region, and a source/drain region on the at least one fin-type active region at at least one side of the gate line. A first conductive plug is connected to the source/drain region and includes cobalt. A second conductive plug is connected to the gate line and spaced apart from the first conductive plug. A third conductive plug is connected to each of the first conductive plug and the second conductive plug. The third conductive plug electrically connects the first conductive plug and the second conductive plug.Type: ApplicationFiled: August 17, 2017Publication date: September 13, 2018Inventors: Joon-gon LEE, Ryuji TOMITA, Do-sun LEE, Chul-sung KIM, Do-hyun LEE
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Publication number: 20180090583Abstract: A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an upper surface in which a recessed region is formed, a contact plug on the source/drain regions and extending in a direction substantially perpendicular to an upper surface of the substrate from an interior of the recessed region, a metal silicide film on an internal surface of the recessed region and including a first portion between a bottom surface of the recessed region and a lower surface of the contact plug and a second portion between a side wall of the recessed region and a side surface of the contact plug, and a metal layer connected to an upper portion of the metal silicide film and on a side surface of a region of the contact plug.Type: ApplicationFiled: March 29, 2017Publication date: March 29, 2018Inventors: Hyo Seok Choi, Ryuji Tomita, Joon Gon Lee, Chul Sung Kim, Jae Eun Lee
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Publication number: 20180090495Abstract: Semiconductor devices may have a first semiconductor element including first active regions that are doped with a first conductivity-type impurity and that are on a semiconductor substrate, a first gate structure between the first active regions, and first contacts connected to the first active regions, respectively; and a second semiconductor element including second active regions that are doped with a second conductivity-type impurity different from the first conductivity-type impurity and that are on the semiconductor substrate, a second gate structure between the second active regions, and second contacts connected to the second active regions, respectively, and having a second length greater than a first length of each of the first contacts in a first direction parallel to an upper surface of the semiconductor substrate.Type: ApplicationFiled: March 29, 2017Publication date: March 29, 2018Inventors: Do Sun LEE, Joon Gon LEE, Na Rae KIM, Chul Sung KIM, Do Hyun LEE, Ryuji TOMITA, Sang Jin HYUN
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Patent number: 9728465Abstract: In a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed on a substrate in a first region and a second region, respectively. A first semiconductor pattern including germanium is formed in the first region on the substrate. A first metal layer is formed on the substrate to cover the first semiconductor pattern. A first heat treatment process is performed such that the first semiconductor pattern and the first metal layer react with each other to form a first metal-semiconductor composite pattern in the first region and a semiconductor material of the substrate and the first metal layer react with each other to form a second metal-semiconductor composite pattern in the second region. The first metal-semiconductor composite pattern is removed from the substrate. A second metal layer is formed on the substrate to cover the second metal-semiconductor composite pattern. The second metal layer includes a material different from the first metal layer.Type: GrantFiled: October 2, 2015Date of Patent: August 8, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-Gon Lee, Ryuji Tomita, Sang-Jin Hyun, Kuo Tai Huang
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Publication number: 20170103948Abstract: An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction, a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction, a conductive region on a portion of the at least one fin-shaped active region at one side of the gate line, and a contact plug extending from the conductive region in a third direction, the third direction being perpendicular to a main plane of the substrate, may be provided. The contact plug may include a metal plug, a conductive barrier film on the conductive region, the conductive barrier film surrounding a sidewall and a bottom surface of the metal plug, the conductive barrier film including an N-rich metal nitride film, and a metal silicide film between the conductive region and the conductive barrier film.Type: ApplicationFiled: June 20, 2016Publication date: April 13, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Do-sun LEE, Do-hyun LEE, Chul-sung KIM, Sang-jin HYUN, Joon-gon LEE
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Publication number: 20170033048Abstract: A semiconductor device includes a substrate with lower structures, an insulation layer covering the lower structures on the substrate, a contact hole through the insulation layer partially exposing the substrate, and a contact structure contacting the substrate through the contact hole, the contact structure including a barrier pattern having an upper barrier on an upper portion of a sidewall of the contact hole, and a lower barrier filling a lower portion of the contact hole, and a conductive contact pattern filling an upper portion of the contact hole defined by the upper barrier and the lower barrier.Type: ApplicationFiled: May 26, 2016Publication date: February 2, 2017Inventors: Chang-Hwa KIM, Joon-Gon LEE, Inchan HWANG
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Publication number: 20160133525Abstract: In a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed on a substrate in a first region and a second region, respectively. A first semiconductor pattern including germanium is formed in the first region on the substrate. A first metal layer is formed on the substrate to cover the first semiconductor pattern. A first heat treatment process is performed such that the first semiconductor pattern and the first metal layer react with each other to form a first metal-semiconductor composite pattern in the first region and a semiconductor material of the substrate and the first metal layer react with each other to form a second metal-semiconductor composite pattern in the second region. The first metal-semiconductor composite pattern is removed from the substrate. A second metal layer is formed on the substrate to cover the second metal-semiconductor composite pattern. The second metal layer includes a material different from the first metal layer.Type: ApplicationFiled: October 2, 2015Publication date: May 12, 2016Inventors: Joon-Gon LEE, Ryuji TOMITA, Sang-Jin HYUN, Kuo Tai HUANG
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Patent number: 8530303Abstract: A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.Type: GrantFiled: September 23, 2011Date of Patent: September 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Bum Kim, Chul-Sung Kim, Yu-Gyun Shin, Dae-Yong Kim, Joon-Gon Lee, Kwang-Young Lee