Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.

Abstract: An ultraviolet light-emitting diode includes: a substrate; an n-type semiconductor layer located on the substrate; a mesa arranged on the n-type semiconductor layer and including an active layer and a p-type semiconductor layer; an n-ohmic contact layer coming in contact with the n-type semiconductor layer; a p-ohmic contact layer coming in contact with the p-type semiconductor layer; an n-bump electrically connected to the n-ohmic contact layer; and a p-bump electrically connected to the p-ohmic contact layer, wherein the mesa includes a main branch and a plurality of sub branches extending from the main branch, the n-ohmic contact layer encompasses the mesa and is interposed in an area between the sub branches, and the n-bump and the p-bump respectively cover the upper part and sides of the mesa. Therefore, an optical output can be increased by reducing light loss, and a forward voltage can be lowered.

Abstract: A light emitting diode includes: a first conductivity type semiconductor layer; a mesa including an active layer and a second conductivity type semiconductor layer, the mesa having a groove disposed under some region of the first conductivity type semiconductor layer to expose an edge of the first conductivity type semiconductor layer, the groove exposing the first conductivity type semiconductor layer; a first electrode including a first contact portion electrically connected to the first conductivity type semiconductor layer through the groove; a second electrode disposed between the first electrode and the second conductivity type semiconductor layer and electrically connected to the second conductivity type semiconductor layer; and an upper electrode pad disposed adjacent to the first conductivity type semiconductor layer and connected to the second electrode, wherein the groove has a shape surrounding a region including a center of the mesa and partially open.

Abstract: A display device performs efficient driving by selectively scanning a peripheral area processed to have low resolution. The display device includes a gate driver that scans a first subset of pixel rows in a first scan block including only the peripheral area during a first frame and a second frame, and respectively scan during the first frame and the second frame a second subset of pixel rows and a third subset of pixel rows in a second scan block including the medial area and the peripheral area excluding the foveal area, and scan pixel rows of pixels in a third scan block including the foveal area, the medial area, and the peripheral area during the first frame and the second frame.

Abstract: Exemplary embodiments of the present invention relate to a high-efficiency light emitting diode (LED).

Abstract: The present disclosure relates to a display interface device which can increase display information transmission efficiency and reduce power consumption and EMI, in which a transmission part transmits clock edge information included in a data packet of each channel at a different timing from clock edge information included in data packets of other channels. A reception part detects a clock edge of each channel from the data packet transmitted through each channel, generates an internal clock signal of each channel, synchronized with the detected clock edge, corrects a delay of each channel depending on a result of a logical operation performed on a delayed clock edge of a channel and a clock edge of another channel to further generate an internal clock signal of each channel, and restores the display information from the data packet of each channel using the internal clock signal of each channel.

Abstract: An organic light-emitting diode (OLED) display can include a display panel including sub-pixels; a deterioration sensing unit configured to sense a deterioration state of the display panel; a power supply configured to output a high voltage for driving the sub-pixels; and a timing controller configured to: receive a deterioration sensing result including information on the deterioration state of the display panel from the deterioration sensing unit, continuously vary the high voltage based on the deterioration sensing result received from the deterioration sensing unit, and provide the varied high voltage to the sub-pixels.

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

Abstract: Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity.

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract: Disclosed herein is a vertical type light emitting diode having a mesa including a groove.

Abstract: Various embodiments of the present invention relate to an electronic device comprising: an MST module; a display; a wireless communication module; and a processor, wherein the processor is configured to: identify a location information of the electronic device; identify a request for payment; determine, in response to the request, a payment transmission scheme corresponding to the location information; and transmit, to an external electronic device, payment information related to the payment by using the MST module while varying a data set or transmission period of the payment information according to the payment transmission scheme. Other embodiments that can be recognized through the specification are also possible.

Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality or bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.

Abstract: A reactive power compensator includes a plurality of phase clusters each including plurality of cells and a controller configured to control the plurality of phase clusters. The controller performs control to generate an offset signal through phasor transformation based on respective voltage values and current values of the plurality of phase clusters and to compensate for energy errors between the plurality of phase clusters based on the generated offset signal.

Abstract: An ultraviolet light emitting diode is provided to comprise an n-type semiconductor layer disposed on a substrate; light emitting elements disposed on the n-type semiconductor layer, each comprising an active layer and a p-type semiconductor layer; an n-type ohmic contact layer contacting the n-type semiconductor layer around the micro light emitting elements; p-type ohmic contact layers contacting the p-type semiconductor layers, respectively; an n-bump electrically connecting to the n-type ohmic contact layer; and a p-bump electrically connected to the p-type ohmic contact layers, wherein each of the n-bump and the p-bump is disposed across over a plurality of micro light emitting elements. The micro light emitting elements may be arranged over a wide area of the substrate, and thus light output can be improved and a forward voltage may be lowered, in addition, the n-bump and the p-bump may be formed relatively widely.

Abstract: A reactive power compensator includes a plurality of phase clusters each including a plurality of cells, and a controller configured to control the plurality of phase clusters. When an energy error is generated in each of the plurality of phase clusters, the controller performs control to compensate for the energy error by generating an offset signal having a zero sequence component based on an error energy value of each of the plurality of phase clusters.

Abstract: Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity.

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

Abstract: A reactive power compensator includes a plurality of phase clusters each including plurality of cells and a controller configured to control the plurality of phase clusters. The controller performs control to generate an offset signal through phasor transformation based on respective voltage values and current values of the plurality of phase clusters and to compensate for energy errors between the plurality of phase clusters based on the generated offset signal.