Abstract: Disclosed herein are an apparatus and method for providing a remote work environment. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program performs Virtual Private Network (VPN) authentication in response to a request for remote access to a work network from a user terminal, performs user authentication in order to connect the user terminal that succeeds in VPN authentication to the work network, decrypts the encrypted user data area of the user terminal that is connected to the work network, and provides the remote work environment to the user terminal based on the user data area through the work network.

Abstract: A display device according to an embodiment includes: a substrate; a transistor that is disposed on the substrate; a light emitting diode that is disposed on the substrate, and connected to the transistor; and a passivation layer that is disposed between the transistor and the light emitting diode, wherein a surface step of the passivation layer is within a range of and including 1 nm to 30 nm.

Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Abstract: A display device includes a plurality of pixels including alignment electrodes and light emitting elements disposed between the alignment electrodes, and the alignment electrodes including outer alignment electrodes and center alignment electrodes disposed between the outer alignment electrodes. A distance between the center alignment electrodes is different from a distance between the center alignment electrodes and the outer alignment electrodes.

Abstract: A substrate processing method includes placing a substrate on a spin chuck and rotating the spin chuck around a central axis extending in a first direction; and applying a processing liquid onto the substrate through a nozzle. The nozzle includes a pipe extending in the first direction and through which the processing liquid moves, and a housing surrounding the pipe, and the pipe includes one or more first lower pipe sections, each of whose width in a second direction intersecting the first direction increases and then decreases in a direction toward the substrate.

Abstract: A semiconductor memory device includes a lower stacked structure with lower metal lines on a substrate, an upper stacked structure with an upper metal line on the lower stacked structure, a vertical structure penetrating the upper and lower stacked structures and including a channel layer, a first cutting line through the upper and lower stacked structures, an upper supporter in a recess on the first cutting line, a second cutting line through the upper and lower stacked structures and spaced apart from the first cutting line, a sub-cutting line through the upper stacked structure while at least partially overlapping the vertical structure in the vertical direction, the sub-cutting line being between the first and second cutting lines, top surfaces of the upper supporter and sub-cutting line being coplanar, and a first interlayer insulating layer surrounding a sidewall of each of the upper supporter and the sub-cutting line.

Abstract: The present invention relates to a method for preparing carbon nanotubes, the method including: preparing a support including AlO(OH) by primary heat treatment of Al(OH)3; preparing an active carrier by supporting a mixture including a main catalyst precursor and a cocatalyst precursor on the support; drying the active carrier through multi-stage drying including vacuum drying; preparing a supported catalyst by secondary heat treatment of the dried active support; and preparing carbon nanotubes in the presence of the supported catalyst, and the carbon nanotubes prepared by the method as described above can remarkably improve conductivity.

Abstract: A paste for a reference electrode according to an embodiment of the present disclosure includes silver chloride powder and a carbon-based conductive material. The carbon-based conductive material may include at least one compound selected from the group consisting of carbon nanotubes, graphite, graphene, and carbon black. The reference electrode formed of the paste for a reference electrode according to an exemplary embodiment may provide improved mechanical properties and electrochemical properties.

Abstract: The present technology relates to a storage device. According to the present technology, a memory controller controlling a memory device including a plurality of memory blocks may include an operation controller and a lifetime information controller. The operation controller may control the memory device to receive a write request from a host and perform a write operation on a selected memory block among the plurality of memory blocks. The lifetime information controller may generate lifetime information including a lifetime level of the selected memory block based on an erase and write count of the selected memory block.

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.

Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.

Abstract: A pixel including: a light emitting element; a first transistor connected between a first power source and a second node; a first capacitor connected to a first node or a second node and a third node; a second transistor between the third node and a data line, the second transistor turned on by a first scan signal; a third transistor between the first and second nodes, the third transistor turned on by a second scan signal; a fifth transistor between the first power source and the first transistor, the fifth transistor turned on by a first emission control signal; a sixth transistor between the second node and the light emitting element, the sixth transistor turned on by a second emission control signal; and an eighth transistor between the second node and a second emission control line, the eighth transistor turned on by a fourth scan signal.

Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

Abstract: An image signal processor includes a register and a disparity correction unit. The register stores disparity data obtained from a pattern image data that an image senor generates, and the image sensor includes a plurality of pixels, and each of the pixel includes at least a first photoelectric conversion element and a second photoelectric conversion element. The image sensor generates the pattern image data in response to a pattern image located at a first distance from the image sensor. The disparity correction unit corrects a disparity distortion of an image data based on the disparity data to generate a result image data, and the image senor generates the image data by capturing an object.

Abstract: An electronic device including a touch-enabled display module configured to display a plurality of windows according to a multi-window mode; and a control module configured to displaying on the touch screen a first application window and a second application window according to the multi-window mode, alter the first application window in response to a touchscreen input received via the touch-enabled display, and automatically alter the second application window in response to the alteration of the first application window.

Abstract: Disclosed are a data processing system comprising: a memory system for providing a host with a memory map segment including map pieces; and the host for storing the memory map segment as a host map segment and converting a logical address into a physical address using the host map segment. The memory system stores changed map pieces in a map cache, inserts the changed map pieces in a response to a first command, and provides the host with the response. The host updates the host map segment based on the changed map pieces. When a read command includes a logical address and a physical address, the memory system accesses a memory device using the physical address of the read command according to whether the logical address of the read command is stored in the map cache.

Abstract: A substrate processing apparatus includes a photoresist coater applying a photoresist film on a substrate, a humidifier increasing an amount of moisture in an ambient to which the photoresist film on the substrate is exposed, and an exposer irradiating the photoresist film exposed to the ambient having the increased amount of moisture with light. The humidifier is disposed between the photoresist coater and the exposer.

Abstract: A capsulorhexis device is inserted into an incision site of a cornea to make an incision in an anterior capsule surrounding a crystalline lens. The capsulorhexis device includes a loop having elasticity and conductivity; a moving member having one end fixed and coupled to the loop; an insertion guide configured so that, while the incision is being made in the crystalline lens capsule, a front end thereof is inserted into the incision site of the cornea; and a housing having one end coupled to a rear end of the insertion guide, wherein the loop is housed in the housing and, to make the incision in the crystalline lens capsule, slides in the housing together with the moving member to pass through the insertion guide and be deployed into an anterior chamber of the eye.

Abstract: A memory controller for controlling a memory device which stores logical-to-physical (L2P) segments includes a map data storage and a map manager. The map data storage stores a plurality of physical-to-logical (P2L) segments including mapping information between a physical address of the memory device in which write data is to be stored and a logical address received from a host, in response to a write request received from the host. The map manager updates the L2P segments stored in the memory device, based on target P2L segments corresponding to a write command provided to the memory device, which have a higher priority than the other P2L segments among the plurality of P2L segments. Each of L2P segments includes mapping information between a logical address and a physical address of data stored in the memory device.

Abstract: An emissive display device includes a display area which includes a plurality of pixels, and a driver disposed at a side of the display area, where the driver includes at least two emission signal stages disposed in one row, and an input signal line connected to the emission signal stages, and the at least two emission signal stages are connected to the same input signal line.