Patents by Inventor Joon-Suc Jang
Joon-Suc Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869599Abstract: A nonvolatile memory device includes cell strings commonly connected between bitlines and a source line where the cell strings are grouped into memory blocks. During a precharge period, channels of the cell strings of a selected memory block are precharged by applying a gate induced drain leakage (GIDL) on voltage to gates of GIDL transistors included in the cell strings of the selected memory block where the GIDL on voltage has a voltage level to induce GIDL. During the precharge period, precharge of channels of the cell strings of an unselected memory block are prevented by controlling a gate voltage of GIDL transistors included in the cell strings of the unselected memory block to prevent the GIDL. During a program execution period after the precharge period, memory cells of the selected memory block connected to a selected wordline are programmed by applying a program voltage to the selected wordline.Type: GrantFiled: December 12, 2022Date of Patent: January 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jungmin Park, Kyunghoon Sung, Ilhan Park, Jisang Lee, Joon Suc Jang, Sanghyun Joo
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Publication number: 20230109025Abstract: A nonvolatile memory device includes cell strings commonly connected between bitlines and a source line where the cell strings are grouped into memory blocks. During a precharge period, channels of the cell strings of a selected memory block are precharged by applying a gate induced drain leakage (GIDL) on voltage to gates of GIDL transistors included in the cell strings of the selected memory block where the GIDL on voltage has a voltage level to induce GIDL. During the precharge period, precharge of channels of the cell strings of an unselected memory block are prevented by controlling a gate voltage of GIDL transistors included in the cell strings of the unselected memory block to prevent the GIDL. During a program execution period after the precharge period, memory cells of the selected memory block connected to a selected wordline are programmed by applying a program voltage to the selected wordline.Type: ApplicationFiled: December 12, 2022Publication date: April 6, 2023Inventors: JUNGMIN PARK, Kyunghoon Sung, Ilhan Park, Jisang Lee, Joon Suc Jang, Sanghyun Joo
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Patent number: 11527293Abstract: A nonvolatile memory device includes cell strings commonly connected between bitlines and a source line where the cell strings are grouped into memory blocks. During a precharge period, channels of the cell strings of a selected memory block are precharged by applying a gate induced drain leakage (GIDL) on voltage to gates of GIDL transistors included in the cell strings of the selected memory block where the GIDL on voltage has a voltage level to induce GIDL. During the precharge period, precharge of channels of the cell strings of an unselected memory block are prevented by controlling a gate voltage of GIDL transistors included in the cell strings of the unselected memory block to prevent the GIDL. During a program execution period after the precharge period, memory cells of the selected memory block connected to a selected wordline are programmed by applying a program voltage to the selected wordline.Type: GrantFiled: June 8, 2021Date of Patent: December 13, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jungmin Park, Kyunghoon Sung, Ilhan Park, Jisang Lee, Joon Suc Jang, Sanghyun Joo
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Publication number: 20220115073Abstract: A nonvolatile memory device includes cell strings commonly connected between bitlines and a source line where the cell strings are grouped into memory blocks. During a precharge period, channels of the cell strings of a selected memory block are precharged by applying a gate induced drain leakage (GIDL) on voltage to gates of GIDL transistors included in the cell strings of the selected memory block where the GIDL on voltage has a voltage level to induce GIDL. During the precharge period, precharge of channels of the cell strings of an unselected memory block are prevented by controlling a gate voltage of GIDL transistors included in the cell strings of the unselected memory block to prevent the GIDL. During a program execution period after the precharge period, memory cells of the selected memory block connected to a selected wordline are programmed by applying a program voltage to the selected wordline.Type: ApplicationFiled: June 8, 2021Publication date: April 14, 2022Inventors: JUNGMIN PARK, KYUNGHOON SUNG, ILHAN PARK, JISANG LEE, JOON SUC JANG, SANGHYUN JOO
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Patent number: 10672488Abstract: A memory device includes a page buffer unit including a plurality of latches latching each of a plurality of pieces of dummy data of selected memory cells according to a plurality of dummy signals provided by a word line of the selected memory cells, and a control logic comparing a count value of a first count latch among the plurality of latches with a reference count value, determining whether to count a second count latch other than the first count latch according to a result of the comparison, and correcting a level of a read signal provided by the word line of the selected memory cells in a read operation.Type: GrantFiled: December 2, 2019Date of Patent: June 2, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jin Bae Bang, Joon Suc Jang
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Patent number: 10629259Abstract: A non-volatile memory device includes a page buffer and a control logic. The page buffer includes a plurality of latch sets that latches first results of a plurality of first read operations according to a plurality of read signals. The first read operations identify a single page datum from among a plurality of page data of selected memory cells included in a plurality of memory cells. The control logic selects a portion of the read signals by comparing the first results of the first read operations, and resets remaining read signals that are not selected. The page buffer stores second results of second read operations according to the selected read signals, and third results of third read operations according to the reset remaining read signals.Type: GrantFiled: August 22, 2018Date of Patent: April 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Joon Suc Jang
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Publication number: 20200105355Abstract: A memory device includes a page buffer unit including a plurality of latches latching each of a plurality of pieces of dummy data of selected memory cells according to a plurality of dummy signals provided by a word line of the selected memory cells, and a control logic comparing a count value of a first count latch among the plurality of latches with a reference count value, determining whether to count a second count latch other than the first count latch according to a result of the comparison, and correcting a level of a read signal provided by the word line of the selected memory cells in a read operation.Type: ApplicationFiled: December 2, 2019Publication date: April 2, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jin Bae Bang, Joon Suc Jang
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Patent number: 10573389Abstract: An operating method of a storage device includes a controller: receiving read data from a non-volatile memory; measuring a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data; measuring a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions; dynamically determining operation parameters for the non-volatile memory, based on the measured distribution variation; and transmitting, to the non-volatile memory, an operate command, an address, and at least one operation parameter corresponding to the address.Type: GrantFiled: June 21, 2018Date of Patent: February 25, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-Ha Kim, Suk-Eun Kang, Ji-Su Kim, Seung-Kyung Ro, Dong-Gi Lee, Yun-Jung Lee, Jin-Wook Lee, Hee-Won Lee, Joon-Suc Jang, Young-Ha Choi
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Patent number: 10497453Abstract: A memory device includes a page buffer unit including a plurality of latches latching each of a plurality of pieces of dummy data of selected memory cells according to a plurality of dummy signals provided by a word line of the selected memory cells, and a control logic comparing a count value of a first count latch among the plurality of latches with a reference count value, determining whether to count a second count latch other than the first count latch according to a result of the comparison, and correcting a level of a read signal provided by the word line of the selected memory cells in a read operation.Type: GrantFiled: October 11, 2018Date of Patent: December 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jin Bae Bang, Joon Suc Jang
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Publication number: 20190295671Abstract: A memory device includes a page buffer unit including a plurality of latches latching each of a plurality of pieces of dummy data of selected memory cells according to a plurality of dummy signals provided by a word line of the selected memory cells, and a control logic comparing a count value of a first count latch among the plurality of latches with a reference count value, determining whether to count a second count latch other than the first count latch according to a result of the comparison, and correcting a level of a read signal provided by the word line of the selected memory cells in a read operation.Type: ApplicationFiled: October 11, 2018Publication date: September 26, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Jin Bae BANG, Joon Suc JANG
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Publication number: 20190214092Abstract: A non-volatile memory device includes a page buffer and a control logic. The page buffer includes a plurality of latch sets that latches first results of a plurality of first read operations according to a plurality of read signals. The first read operations identify a single page datum from among a plurality of page data of selected memory cells included in a plurality of memory cells. The control logic selects a portion of the read signals by comparing the first results of the first read operations, and resets remaining read signals that are not selected. The page buffer stores second results of second read operations according to the selected read signals, and third results of third read operations according to the reset remaining read signals.Type: ApplicationFiled: August 22, 2018Publication date: July 11, 2019Inventor: JOON SUC JANG
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Publication number: 20190115078Abstract: An operating method of a storage device includes a controller: receiving read data from a non-volatile memory; measuring a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data; measuring a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions; dynamically determining operation parameters for the non-volatile memory, based on the measured distribution variation; and transmitting, to the non-volatile memory, an operate command, an address, and at least one operation parameter corresponding to the address.Type: ApplicationFiled: June 21, 2018Publication date: April 18, 2019Inventors: CHAN-HA KIM, SUK-EUN KANG, JI-SU KIM, SEUNG-KYUNG RO, DONG-GI LEE, YUN-JUNG LEE, JIN-WOOK LEE, HEE-WON LEE, JOON-SUC JANG, YOUNG-HA CHOI
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Patent number: 9921749Abstract: A method of operating a memory system, including a memory device, includes managing program order information of the memory device based on a program order stamp (POS) indicating a relative temporal relationship between program operations of a plurality of memory groups that are included in the memory device. The method includes generating a first mapping table that stores a read voltage offset and an upper POS corresponding to the read voltage offset, by using a plurality of voltage levels that are sequentially decreased or reduced, and generating a second mapping table that stores the read voltage offset and a lower POS corresponding to the read voltage offset, by using a plurality of voltage levels that are sequentially increased. A read voltage for performing a read operation on the memory device is variably determined based on the first and second mapping tables and the program order information.Type: GrantFiled: June 18, 2015Date of Patent: March 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Ryun Kim, Joon-Suc Jang
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Patent number: 9852795Abstract: A method of operating a nonvolatile memory device includes performing a first memory operation on a first memory block of a plurality of memory blocks and a curing operation on a portion of the first memory block when a status signal indicates a ready state of the nonvolatile memory device during an interval equal to or greater than a reference interval after the first memory operation is completed. The nonvolatile memory device includes the plurality of memory blocks, each memory block including a plurality of vertical strings extending in a vertical direction with respect to a substrate.Type: GrantFiled: September 22, 2016Date of Patent: December 26, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Ku Kang, Sang-Yong Yoon, Joon-Suc Jang
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Patent number: 9818475Abstract: In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data.Type: GrantFiled: January 21, 2016Date of Patent: November 14, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Suc Jang, Dong-Hun Kwak
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Publication number: 20170092361Abstract: A method of operating a nonvolatile memory device includes performing a first memory operation on a first memory block of a plurality of memory blocks and a curing operation on a portion of the first memory block when a status signal indicates a ready state of the nonvolatile memory device during an interval equal to or greater than a reference interval after the first memory operation is completed. The nonvolatile memory device includes the plurality of memory blocks, each memory block including a plurality of vertical strings extending in a vertical direction with respect to a substrate.Type: ApplicationFiled: September 22, 2016Publication date: March 30, 2017Inventors: DONG-KU KANG, SANG-YONG YOON, JOON-SUC JANG
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Publication number: 20160141025Abstract: In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data.Type: ApplicationFiled: January 21, 2016Publication date: May 19, 2016Inventors: Joon-Suc Jang, Dong-Hun Kwak
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Publication number: 20160124642Abstract: A method of operating a memory system, including a memory device, includes managing program order information of the memory device based on a program order stamp (POS) indicating a relative temporal relationship between program operations of a plurality of memory groups that are included in the memory device. The method includes generating a first mapping table that stores a read voltage offset and an upper POS corresponding to the read voltage offset, by using a plurality of voltage levels that are sequentially reduced, and generating a second mapping table that stores the read voltage offset and a lower POS corresponding to the read voltage offset, by using a plurality of voltage levels that are sequentially increased. Furthermore, a read voltage for performing a read operation on the memory device is variably determined based on the first and second mapping tables and the program order information.Type: ApplicationFiled: June 18, 2015Publication date: May 5, 2016Inventors: KYUNG-RYUN KIM, JOON-SUC JANG
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Patent number: 9281069Abstract: In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data.Type: GrantFiled: May 9, 2014Date of Patent: March 8, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-Suc Jang, Dong-Hun Kwak
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Publication number: 20140247657Abstract: In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data.Type: ApplicationFiled: May 9, 2014Publication date: September 4, 2014Inventors: Joon-Suc JANG, Dong-Hun KWAK