Abstract: An embedded logic analyzer of an integrated circuit includes a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions; an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing; and packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal.

Abstract: An embedded logic analyzer of an integrated circuit includes a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions; an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing; and packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal.

Abstract: An embedded logic analyzer of an integrated circuit includes a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions; an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing; and packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal.

Abstract: A storage device, method for processing a plurality of pieces of client data, and a chipset are provided. The storage device includes a first stage storage unit configured to receive the plurality of pieces of client data generated in bursts from a plurality of clients and store the received plurality of pieces of client data; a second stage storage unit configured to receive the plurality of pieces of client data from the first stage storage unit and store the received plurality of pieces of client data in a plurality of memory banks shared by the plurality of clients, respectively, in bursts; and a third stage storage unit configured to receive each of the plurality of pieces of client data from the second stage storage unit and store data of a transaction unit corresponding to a transmission unit for data processing.

Abstract: An embedded logic analyzer of an integrated circuit includes a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions; an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing; and packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal.

Abstract: A storage device, method for processing a plurality of pieces of client data, and a chipset are provided. The storage device includes a first stage storage unit configured to receive the plurality of pieces of client data generated in bursts from a plurality of clients and store the received plurality of pieces of client data; a second stage storage unit configured to receive the plurality of pieces of client data from the first stage storage unit and store the received plurality of pieces of client data in a plurality of memory banks shared by the plurality of clients, respectively, in bursts; and a third stage storage unit configured to receive each of the plurality of pieces of client data from the second stage storage unit and store data of a transaction unit corresponding to a transmission unit for data processing.

Abstract: An apparatus and method for receiving a broadcasting service in a digital multimedia broadcasting (DMB) system. In a method for changing a broadcasting service in a terminal for receiving DMB services, it is determined if a reserved decoding resource element is present while data of a first broadcasting service is decoded and output. If the reserved decoding resource element is present, it is determined if an operation for decoding a pilot channel will be stopped. If the operation for decoding the pilot channel is stopped, data of a second broadcasting service is received and decoded using the reserved decoding resource element and a decoding resource element for decoding the pilot channel. When a user makes a change to the second broadcasting service, the data of the first and second broadcasting services is simultaneously output.