Patents by Inventor Joong Yang
Joong Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11387270Abstract: An image sensor package includes a substrate, an image sensor mounted on the substrate, a bonding wire connecting the image sensor to the substrate, a reflector disposed on the image sensor, a sealing member sealing the bonding wire and a portion of the image sensor, and covering at least a portion of the reflector, the sealing member including a hole exposing an effective imaging plane of the image sensor, and a filter attached to the sealing member.Type: GrantFiled: August 8, 2019Date of Patent: July 12, 2022Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Do Jae Yoo, Byoung Heon Kim, Yong Gil Namgung, Jong Cheol Hong, Si Joong Yang
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Publication number: 20200395396Abstract: An image sensor package includes a substrate; an image sensor connected to the substrate; a film member disposed on the substrate and defining a hole for exposing an effective image pickup surface of the image sensor; a bonding wire connecting the image sensor to the substrate; and a filter attached to the film member. The film member includes at least one void therein and at least a portion of the bonding wire is contained within the film member.Type: ApplicationFiled: December 18, 2019Publication date: December 17, 2020Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Do Jae YOO, Hye Ran WEE, Soon Kyo LEE, Jong Cheol HONG, Si Joong YANG
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Publication number: 20200350351Abstract: An image sensor package includes a substrate, an image sensor mounted on the substrate, a bonding wire connecting the image sensor to the substrate, a reflector disposed on the image sensor, a sealing member sealing the bonding wire and a portion of the image sensor, and covering at least a portion of the reflector, the sealing member including a hole exposing an effective imaging plane of the image sensor, and a filter attached to the sealing member.Type: ApplicationFiled: August 8, 2019Publication date: November 5, 2020Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Do Jae YOO, Byoung Heon KIM, Yong Gil NAMGUNG, Jong Cheol HONG, Si Joong YANG
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Patent number: 9455207Abstract: Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and a plurality of lead members integrally formed with the housing and electrically connecting the plurality of first semiconductor devices and the substrate. According to the present invention, reliability can be improved by increasing bonding areas and bonding strength of semiconductor devices as well as processibilty can be enhanced and failure is reduced by adjusting a step difference with respect to an arrangement and height of the semiconductor devices. Further, a processing time resulting from an omission of a wire bonding process is reduced.Type: GrantFiled: March 14, 2013Date of Patent: September 27, 2016Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Kwang Soo Kim, Si Joong Yang, Bum Seok Suh, Young Hoon Kwak, Job Ha
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Patent number: 9123688Abstract: Disclosed herein is a semiconductor module package, including: a first module including a first heat radiation substrate and one or more first semiconductor elements and having a first N terminal and a first P terminal formed at one end thereof; a second module including a second heat radiation substrate and one or more second semiconductor elements, having a second N terminal and a second P terminal formed at one end thereof, and disposed so as to face the first module; and a first output terminal formed by electrically connecting the first module to the second module.Type: GrantFiled: October 1, 2013Date of Patent: September 1, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Tae Hyun Kim, Bum Seok Suh, Joon Hyung Cho, Si Joong Yang
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Publication number: 20150091146Abstract: Disclosed herein is a power semiconductor package. The power semiconductor package according to a preferred embodiment of the present invention includes: a semiconductor device; a circuit pattern formed on the semiconductor device; a molding member burying the semiconductor device and the circuit pattern and formed so as to expose one surface of the circuit pattern; and a heat radiating member adhered to the circuit pattern exposed by the molding member and formed of a non-conductive material.Type: ApplicationFiled: May 27, 2014Publication date: April 2, 2015Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Kyu Hwan Oh, Si Joong Yang, Do Jae Yoo, Young Hoon Kwak
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Publication number: 20140183717Abstract: Disclosed herein is a semiconductor module package, including: a first module including a first heat radiation substrate and one or more first semiconductor elements and having a first N terminal and a first P terminal formed at one end thereof; a second module including a second heat radiation substrate and one or more second semiconductor elements, having a second N terminal and a second P terminal formed at one end thereof, and disposed so as to face the first module; and a first output terminal formed by electrically connecting the first module to the second module.Type: ApplicationFiled: October 1, 2013Publication date: July 3, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Tae Hyun Kim, Bum Seok Suh, Joon Hyung Cho, Si Joong Yang
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Publication number: 20140110833Abstract: Disclosed herein is a power module package. The power module package includes a substrate having one surface formed with a circuit pattern including a chip mounting pad and an external connection pad and the other surface; a semiconductor chip mounted on the chip mounting pad; and an external connection terminal having one terminal and the other terminal, the one terminal being connected to the external connection pad and the other terminal protruding to the outside, in which the external connection pad and the external connection terminal are bonded to each other by welding.Type: ApplicationFiled: October 22, 2013Publication date: April 24, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Do Jae Yoo, Si Joong Yang
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Publication number: 20140035157Abstract: There is provided a semiconductor package including: at least one internal lead having at least one electronic component mounted on a surface thereof; a molding unit sealing the electronic component and the internal lead; at least one external lead extending from the internal lead and protruding outwardly from ends of the molding unit; and a stopper provided on the external lead.Type: ApplicationFiled: November 29, 2012Publication date: February 6, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Si Joong YANG, Joon Seok CHAE, Tae Hyun KIM, Suk Ho LEE
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Publication number: 20140029201Abstract: There is provided a power package module, including: a lead frame; at least one first electronic component mounted on the lead frame; and an insulating member disposed on a first surface of the first electronic component and having a via electrode connected to the first electronic component.Type: ApplicationFiled: September 14, 2012Publication date: January 30, 2014Inventors: Si Joong YANG, Do Jae Yoo, Joon Seok Chae
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Publication number: 20120125096Abstract: Disclosed herein is an inertial sensor which includes a sensing unit including a mass mounted to be displaced on a flexible substrate part, a driving unit moving the mass, and a displacement detecting unit detecting a displacement of the mass, the inertial sensor comprising: a top cap covering a top of the flexible substrate part; and a bottom cap covering a bottom of the mass. Thereby, the inertial sensor can be implemented in an economic EMC molding package shape, while protecting the mass and the piezo-electric element. Further, the inertial sensor optimizes a thickness of the cap covering the mass and the piezo-electric element and an interval between the mass and the piezo-electric element to have improved freedom in design of space utilization as well as improved driving characteristics and Q values.Type: ApplicationFiled: October 27, 2011Publication date: May 24, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Heung Woo Park, Won Kyu Jeung, Hyun Kee Lee, Si Joong Yang
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Publication number: 20110012220Abstract: A wafer-level image sensor module including: a wafer having an image sensor and a plurality of upper pads provided thereon, the wafer having an inclined surface on either side thereof; a transparent member installed above the top surface of the wafer so as to seal the image sensor; a plurality of lead portions having one ends connected to the respective upper pads, the lead portions being formed to extend to the bottom surface of the wafer along the inclined surface of the wafer; an encapsulation portion formed on the top surface of the wafer so as to be positioned outside the transparent member; and a plurality of external connection members that are electrically connected to the other ends of the respective lead portionsType: ApplicationFiled: September 22, 2010Publication date: January 20, 2011Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook Park, Jing Li Yuan, Ju Pyo Hong, Si Joong Yang
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Patent number: 7696004Abstract: Provided is a wafer level package fabrication method. The method includes providing a device substrate wafer including one or more devices on an upper surface thereof, and a bonding pad electrically connected to the device, providing a bonding seal surrounding the device along the bonding pad, bonding a cap substrate wafer to the device substrate wafer through the bonding seal, the cap substrate wafer having a via formed in a region corresponding to the bonding pad, forming an external terminal on the cap substrate wafer, the external terminal being electrically connected to the bonding pad, and cutting the cap substrate wafer and the device substrate wafer along a cutting line to individually separate a plurality of wafer level packages. The method is conducive to reducing product size for miniaturization, is capable of performing a bonding process without wafer deformation or damage, and increases freedom in wafer material selection.Type: GrantFiled: June 2, 2008Date of Patent: April 13, 2010Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jingli Yuan, Jae Cheon Doh, Si Joong Yang, In Goo Kang, Seung Wook Park
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Patent number: 7670878Abstract: Provided is a method for manufacturing a semiconductor package. In the method, a wafer for a cap substrate is provided. The wafer for the cap substrate includes a plurality of vias and via electrodes on a lower surface. A wafer for a device substrate is provided. The wafer for the device substrate includes a circuit unit and a connection electrode on an upper surface. The wafer for the cap substrate and the wafer for the device substrate are primarily bonded by a medium of a primary adhesive. A trench is formed to expose the upper surface of the wafer for the device substrate to an outside along an outer edge of the primary adhesive. A secondary bonding operation is performed by a medium of a secondary adhesive to electrically connect the via electrode and the connection electrode. The wafer for the device substrate is diced along a virtual cut line.Type: GrantFiled: May 16, 2008Date of Patent: March 2, 2010Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jing Li Yuan, Jae Cheon Doh, Tae Hoon Kim, Si Joong Yang, Seung Wook Park
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Publication number: 20090085204Abstract: Provided is a wafer-level package including a wafer-level semiconductor chip having a plurality of integrated circuits (ICs) and pads formed on the top surface thereof; a molding material of which the outer portion is supported by the top surface of the semiconductor chip such that a cavity is provided on the semiconductor chip; and a conducive member filled in a plurality of vias which are formed in arbitrary positions of the molding material so as to pass through the molding material, the conductive member being connected to the pads.Type: ApplicationFiled: July 8, 2008Publication date: April 2, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook Park, Chun Choi, Ju Pyo Hong, Si Joong Yang, Dae Jun Kim
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Publication number: 20090085134Abstract: Provided is a wafer-level image sensor module including a wafer; an image sensor mounted on the wafer; a transparent member installed above the top surface of the wafer so as to seal the image sensor; a plurality of vias formed in the wafer so as to be positioned outside the transparent member; a plurality of upper pads formed on the upper ends of the respective vias; an encapsulation portion formed on the top surface of the wafer so as to be positioned outside the transparent member; and a plurality of external connection members that are electrically connected to the lower ends of the respective vias.Type: ApplicationFiled: January 17, 2008Publication date: April 2, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook Park, Jing Li Yuan, Ju Pyo Hong, Si Joong Yang
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Publication number: 20080299706Abstract: Provided is a wafer level package fabrication method. The method includes providing a device substrate wafer including one or more devices on an upper surface thereof, and a bonding pad electrically connected to the device, providing a bonding seal surrounding the device along the bonding pad, bonding a cap substrate wafer to the device substrate wafer through the bonding seal, the cap substrate wafer having a via formed in a region corresponding to the bonding pad, forming an external terminal on the cap substrate wafer, the external terminal being electrically connected to the bonding pad, and cutting the cap substrate wafer and the device substrate wafer along a cutting line to individually separate a plurality of wafer level packages. The method is conducive to reducing product size for miniaturization, is capable of performing a bonding process without wafer deformation or damage, and increases freedom in wafer material selection.Type: ApplicationFiled: June 2, 2008Publication date: December 4, 2008Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jingli Yuan, Jae Cheon Doh, Si Joong Yang, In Goo Kang, Seung Wook Park
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Patent number: D703625Type: GrantFiled: March 18, 2013Date of Patent: April 29, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jae Hyun Lim, Young Ki Lee, Tae Hyun Kim, Si Joong Yang, Jong Man Kim, Kyu Kwan Oh, Young Ho Sohn
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Patent number: D719113Type: GrantFiled: March 18, 2013Date of Patent: December 9, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Young Ho Sohn, Si Joong Yang, Young Ki Lee, Jin Su Kim, Dong Hwan Kim, Jong Man Kim, Kee Ju Um, Hyo Jin Lee, Young Hoon Kwak
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Patent number: D719926Type: GrantFiled: March 18, 2013Date of Patent: December 23, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Young Ho Sohn, Si Joong Yang, Young Ki Lee, Jin Su Kim, Dong Hwan Kim, Jong Man Kim, Kee Ju Um, Hyo Jin Lee, Young Hoon Kwak