Abstract: A test board is provided. The test board comprises a first region which includes a first upper surface with first test sockets aligned thereon, and a first lower surface opposite to the first upper surface, a second region which includes a second upper surface with second test sockets aligned thereon, and a second lower surface opposite to the second upper surface, a hinge portion between the first region and the second region, and configured to connect the first region and the second region such that the first region and the second region are folded or unfolded, a first connector at one end of the first region opposite to the hinge portion and a second connector at one end of the second region opposite to the hinge portion.

Abstract: Provided are a test board and a test system for efficiently testing a semiconductor package, and a manufacturing method for the semiconductor package using the same. A test apparatus includes a field programmable gate array (FPGA) configured to output a first data signal to be transmitted to the semiconductor device and a second data signal to be transmitted to the semiconductor device and a memory configured to store a test result. The FPGA includes a first input/output block configured to output the first data signal, a second input/output block configured to output the second data signal, a serializer/deserializer (SerDes) circuit configured to generate a strobe signal, and a skew calibration input/output block configured to receive the first data signal from the first input/output block, the second data signal from the second input/output block, and the strobe signal from the SerDes circuit.

Abstract: Provided are a test board and a test system for efficiently testing a semiconductor package, and a manufacturing method for the semiconductor package using the same. A test apparatus includes a field programmable gate array (FPGA) configured to output a first data signal to be transmitted to the semiconductor device and a second data signal to be transmitted to the semiconductor device and a memory configured to store a test result. The FPGA includes a first input/output block configured to output the first data signal, a second input/output block configured to output the second data signal, a serializer/deserializer (SerDes) circuit configured to generate a strobe signal, and a skew calibration input/output block configured to receive the first data signal from the first input/output block, the second data signal from the second input/output block, and the strobe signal from the SerDes circuit.

Abstract: A test interface board includes an encoder, a signal copier, and a decoder. The encoder digitally encodes test data to generate a modulation signal. The signal copier copies the modulation signal by inductively coupling the modulation signal and outputs at least one copy signal corresponding to the modulation signal. The decoder decodes the modulation signal and the at least one copy signal in order to test at least two semiconductor devices.

Abstract: A test board includes: a board substrate; a device under test (DUT) socket connected to the board substrate and configured to accommodate a semiconductor package; a test controller; a wireless signal unit configured to wirelessly exchange signals with a server; and a wireless power unit configured to be wirelessly charged by an external source and configured to supply electric power to the test controller and the DUT socket, wherein the test controller is configured to independently perform a test on the semiconductor package accommodated in the DUT socket in response to a test pattern command being wirelessly received from the server via the wireless signal unit.

Abstract: A test board includes: a board substrate; a device under test (DUT) socket connected to the board substrate and configured to accommodate a semiconductor package; a test controller; a wireless signal unit configured to wirelessly exchange signals with a server; and a wireless power unit configured to be wirelessly charged by an external source and configured to supply electric power to the test controller and the DUT socket, wherein the test controller is configured to independently perform a test on the semiconductor package accommodated in the DUT socket in response to a test pattern command being wirelessly received from the server via the wireless signal unit.

Abstract: A test interface board includes an encoder, a signal copier, and a decoder. The encoder digitally encodes test data to generate a modulation signal. The signal copier copies the modulation signal by inductively coupling the modulation signal and outputs at least one copy signal corresponding to the modulation signal. The decoder decodes the modulation signal and the at least one copy signal in order to test at least two semiconductor devices.