Abstract: A system-on-a-chip includes a first digital domain and a second digital domain. An interface circuit includes a level-shifting circuit for converting a signal between the first digital domain and the second digital domain. The first digital domain includes a control circuit configured to generate a control signal for transmission to the second digital domain. The control signal includes a pulse having a nominal duration adapted to the level-shifting circuit. At the input of the level-shifting circuit, the interface circuit includes, in the first domain, a conditional pulse-stretching circuit that lengthens a duration of the pulse of the control signal to at least the nominal duration when a duration of the pulse of the control signal is shorter than the nominal duration and non-zero.

Abstract: A method is presented for monitoring a tampering state of closed container wherein a first electrically conductive wire extends across a slot between two portions of the closed container. The method includes applying a voltage across the first electrically conductive wire, sensing a voltage at one end of the first electrically conductive wire, and generating a signal indicating the tampering state of the closed container in response to the sensed voltage. The sensed voltage has a first voltage value if the first electrically conductive wire has been severed by tampering, and this tampered state is then reported using near field communication. The near field communication is blocked if it is sensed that the severed first electrically conductive wire has been repaired.

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

Abstract: A closed container includes a detection device for detecting opening of or an attempt to open the container. The detection device includes a contactless passive transponder that is configured to communicate with a reader via an antenna using a carrier signal. An integrated circuit of the transponder includes two input terminals connected to the antenna and two output terminals linked by a first electrically conductive wire having a severable part which is severed in the event of an opening of or an attempted opening of the container. A shorting circuit is configured to short-circuit a first output terminal with a first input terminal in the event of a conductive repair of the severed part which forms an electrical connection between the two output terminals.

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

Abstract: An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.

Abstract: An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

Abstract: A closed container includes a detection device for detecting opening of or an attempt to open the container. The detection device includes a contactless passive transponder that is configured to communicate with a reader via an antenna using a carrier signal. An integrated circuit of the transponder includes two input terminals connected to the antenna and two output terminals linked by a first electrically conductive wire having a severable part which is severed in the event of an opening of or an attempted opening of the container. A shorting circuit is configured to short-circuit a first output terminal with a first input terminal in the event of a conductive repair of the severed part which forms an electrical connection between the two output terminals.