Abstract: Method for analyzing and synthesizing pulses using a first pulse state memory for storing the pulse state connected to a pulse edge detector for detecting a pulse change of state, the latter connected to the reset pin of a pulse counter driven by a clock; a first-in-first-out memory connected to the counter for receiving the counter content for each pulse, and a microprocessor connected to the first-in-first-out memory output, having a signal pulse list for storing for each pulse its state and pulse length measured in clock counts. Two or more associate memories are provided for storing clock count of any 0-state pulse and any 1-state pulse, and a pulse display connected to each associate memory to display any 0-state pulse and any 1-state pulse as a percentage of the total pulse period To.

Abstract: A modulator for modulating binary data signals by frequency shift keying (FSK), in which a binary data level 1 is represented by a first frequency (f.sub.1) and the binary data level 0 is represented by a second frequency (f.sub.2) is provided. The modulator addresses a first addressing input of a programmable memory with the binary data signals, in which half the periods of the two frequencies (f.sub.1, f.sub.2) are marked in two memory regions (I, II) of the programmable memory addressed by the first addressing input. The modulator further controls other address inputs with a driven counter; and generates a pulse resetting the counter and controlling a 2:1 frequency divider having an output delivering one of the frequencies (f.sub.1, f.sub.2), when addressing a storage cell, in which one of the halfperiods is marked.