Abstract: A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. Each page of a graphics texture has an associated fade factor value that can be set by an application that is to use the texture to control the contribution that the page will be used to make to any texturing result that is generated using the texture page in question. The graphics processing system then controls the contribution of texture data from a texture page to texturing result data to be generated in accordance with the fade factor value associated with the texture page in question. This allows texture paging to be done in a more visually pleasing manner than just a binary “page-is-here”/“page-is-not-here” switch.

Abstract: A data processing system is used to evaluate a data processing function by executing a sequence of program instructions including an intermediate value generating instruction Inst0 and an intermediate value consuming instruction Inst1. In dependence upon one or more input operands to the evaluation, an embedded opcode within the intermediate value passed between the intermediate value generating instruction and the intermediate value consuming instruction may be set to have a value indicating that a substitute instruction should be used in place of the intermediate value consuming instruction. The instructions may be floating point instructions, such as a floating point power instruction evaluating the data processing function ab.

Abstract: Each block of texture data elements is encoded as a block of texture data. The encoding process includes determining for each block of texture data elements whether the set of texture data elements of the block all have sufficiently similar data values. If they do, the extent of a region within the texture including the block in which every texture data element has sufficiently similar data values is then determined, and an encoded texture data block to represent the block of texture data elements that indicates that the block specifies a region within the texture in which every texture data element is to be allocated the same data value when decoded, and that includes data indicating the constant data value for the block and data indicating the extent of the region within the texture that the block relates to, is generated.

Abstract: A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.

Abstract: A texture map for use in graphics processing is encoded by first subdividing the texture map into a plurality of texture element blocks. The texture data elements in each texel block to be encoded are then divided into different partitions (sub sets) within the block. The partitioned block is then encoded in a compressed form as an encoded texture data block. Each encoded block is partitioned using a partitioning pattern generation function to generate the partitioning patterns. The partitioning pattern generation function sorts the texture data elements of the block into respective partitions based on their respective positions within the block. To do this the partitioning pattern generation function generates a series of sawtooth waves at various angles, phases and frequencies across the block of texture data elements to be encoded.

Abstract: A graphics processing system generates interpolated vertex shaded attribute data for plural sampling points of plural fragments of a quad fragment that is being used to sample a primitive. The interpolated vertex shaded attribute data for the plural sampling points is generated using a reference position for the quad fragment that is defined with respect to a first coordinate system, together with rotated sampling point delta values for the primitive that are defined with respect to a second coordinate system. The rotated sampling point delta values allow the interpolated vertex shaded attribute data to be generated more efficiently for the plural sampling points.

Abstract: A graphics processing pipeline comprises a tessellation stage that is configured to tessellate a patch into tessellation primitives. When tessellating the patch, the tessellation stage generates tessellation vertex coordinate pairs that define within a parameter space the locations of vertices of the tessellation primitives for the patch. The tessellation vertex coordinate pairs are initially represented using a first binary representation and are then encoded into a more convenient second binary representation, but without any loss of resolution in the data. The step of encoding comprises mapping at least one of the tessellation vertex coordinate pairs to a mapped coordinate pair that can be represented using the second binary representation, wherein the mapped coordinate pair defines a location within an area of the parameter space that would otherwise be unused, invalid and/or unreachable for the vertices of the tessellation primitives for the patch.

Abstract: In a graphics processor, the rasteriser operates to identify pairs of fragments for a primitive being rendered for which not all the sampling positions in the fragments are covered by the primitive. When the fragments reach the fragment shader, corresponding execution threads are spawned for execution by the fragment shader to process the fragments. A first part of the fragment shader program that uses the helper threads of the thread groups is then executed. There is then a merge instruction in the fragment shader program which operates to cause the active threads of the thread groups to be merged into a single, combined thread group. Following this thread group merger, the remaining program steps of the fragment shader program are executed for the merged thread group.

Abstract: A programmable execution unit of a graphics processor that executes program instructions to perform graphics shading operations can use at least two different register file mapping configurations for mapping registers to execution threads. When a shader program is to be executed, how the shader program will use the registers is considered and the register file mapping configuration to use for the shader program is then selected based on the assessment of the register use by the shader program. Appropriate state information is then set to cause the threads being executed by the programmable execution unit to use the registers according to the selected register file mapping configuration when executing the shader program.

Abstract: A graphics processing pipeline 1 includes a rasteriser 3 that tests patches representing respective different regions of a render output against the edges of primitives 2 to determine if the primitive at least partially covers the patch and an early depth test stage 4 that performs early depth tests for primitives in respect of patches of the render output that the primitive has been found by the rasteriser at least partially to cover, by using depth test information 5 associated with a patch indicating the number and distribution of different depth value regions associated with the patch to determine the depth value region or regions associated with the patch that the primitive should be depth tested against, and then performing a depth test or tests for the primitive in respect of the respective determined depth value region or regions associated with the patch.

Abstract: A graphics processing unit 3 includes a rasteriser 25, a thread spawner 40, a programmable execution unit 41, a varying interpolator 42, a texture mapper 43, and a blender 29. The programmable execution unit 41 is able to communicate with the varying interpolator 42, the texture mapper 43 and the blender 29 to request processing operations by those graphic specific accelerators. In addition to this, these graphics-specific accelerators are also able to communicate directly with each other and with the thread spawner 40, independently of the programmable execution unit 41. This allows for certain graphics processing operations to be performed using direct communication between the graphics-specific accelerators of the graphics processing unit, instead of executing instructions in the programmable execution unit to trigger the performance of those operations by the graphics-specific accelerators.

Abstract: An apparatus and method are provided for controlling rounding when performing a floating point operation. The apparatus has argument reduction circuitry to perform an argument reduction operation, and in addition provides reduce and round circuitry that generates from a supplied floating point value a modified floating point value to be input to the argument reduction circuitry. The reduce and round circuitry is arranged to modify a significand of the supplied floating point value, based on a specified value N, in order to produce a truncated significand with a specified rounding applied, the truncated significand being N bits shorter than the significand of the supplied floating point value, and then being used as a significand for the modified floating point value. The specified value N is chosen such that the argument reduction operation performed using the modified floating point value will inhibit roundoff error in a result of the argument reduction operation.

Abstract: An apparatus and method are provided, the apparatus comprising: storage circuitry to store an input data value; divider circuitry to split the input data value into at least one sub-value in dependence on a number of lanes for a current iteration, each sub-value occupying a lane, and to operate on each sub-value to generate a quotient corresponding to the division of that sub-value by a divisor, wherein the divisor is an odd integer; remainder circuitry to operate on each sub-value to generate a remainder corresponding to the remainder of dividing that sub-value by the divisor; concatenation circuitry to concatenate each quotient to produce a concatenated division value, and to concatenate each remainder to produce a concatenated remainder value, in each subsequent iteration, the input data value being formed from the concatenated remainder value of a preceding iteration; and output circuitry to output, after a plurality of iterations, a result of adding the concatenated division values produced by said plura

Abstract: Operating a graphics processing pipeline that includes processing stages including a rasteriser that rasterises input primitives to generate graphics fragments to be processed, each graphics fragment having one or more sampling points associated with it, and a renderer that processes fragments generated by the rasteriser to generate output fragment data for output to a render output, comprising the following steps: (i) determining first information to test whether at least a part of a primitive should be processed further; (ii) using at least some of the first information to decide whether to process at least a part of the primitive further; and if it is decided that at least a part of the primitive is to be processed further: (iii) determining further information to be used in further processing of the primitive; and (iv) further processing at least a part of the primitive using the determined further information.

Abstract: A data processing system includes an execution pipeline that includes one or more programmable execution stages which execute execution threads to execute instructions to perform data processing operations. Instructions to be executed by a group of execution threads are first fetched into an instruction cache and then read from the instruction cache for execution by the thread group. When an instruction to be executed by a thread group is present in a cache line in the instruction cache, or is to be fetched into an allocated cache line in the instruction cache, a pointer to the location of the instruction in the instruction cache is stored for the thread group. This stored pointer is then used to retrieve the instruction for execution by the thread group from the instruction cache.

Abstract: Techniques for performing clipping of graphics primitives 60 with respect to a clipping boundary 65 are described. The clipping step 10 may be performed separately for each tile of a graphics frame to be rendered, after a primitive list for the tile has been read from a primitive memory 38. Clipping may be performed only for larger primitives whose size exceeds a given threshold. Clipping of a primitive 60 to the clipping boundary 65 may be performed inexactly so that only a single clipped primitive is generated which may extend beyond the clipping boundary. A clipped primitive generated by clipping may be used for a depth function calculation of a primitive setup operation and not for an edge determination.

Abstract: Each block of texture data elements is encoded as a block of texture data that includes: data indicating how to generate a set of data values to be used to generate data values for a set of the texture data elements that the block represents; data indicating a set of integer values to be used to generate the set of data values to be used to generate data values for a set of the texture data elements that the block represents; data indicating a set of index values indicating how to use the generated set of data values to generate data values for texture data elements of the set of texture data elements that the generated set of data values is to be used for; and data indicating the indexing scheme that has been used for the block.

Abstract: When encoding a texture map 1 for use in graphics processing, the texture map is divided into a plurality of equal-sized blocks 2 of texture data elements. Each block 2 of texture data elements is then encoded as a block of texture data 5 that includes a set of integer values to be used to generate a set of base data values for the block, and a set of index values indicating how to use the base data values to generate data values for the texture data elements that the block represents. The integer values and the index values are both encoded in an encoded texture data block using a combination of base-n values, where n is greater than two, and base-2 values. Predefined bit representations are used to represent plural base-n values (n>2) collectively, and the bits of the bit representations representing the base-n values (n>2) are interleaved with bits representing the base-2 values in the encoded texture data block.

Abstract: An apparatus and method are provided for inhibiting roundoff error in a floating point argument reduction operation. The apparatus has reciprocal estimation circuitry that is responsive to a first floating point value to determine a second floating point value that is an estimated reciprocal of the first floating point value. During this determination, the second floating point value has both its magnitude and its error bound constrained in dependence on a specified value N. Argument reduction circuitry then performs an argument reduction operation using the first and second floating point values as inputs, in order to generate a third floating point value. The use of the specified value N to constrain both the magnitude and the error bound of the second floating point value causes roundoff error to be inhibited in the third floating point value that is generated by the argument reduction operation.

Abstract: A rasterizer and a method of performing rasterization in a graphics processing pipeline are disclosed. A rasterizer of a graphics processing pipeline tests larger patches of a render output to be generated against a primitive to be rasterized, to determine if the primitive covers (at least in part) any smaller patches of the render output that the larger patch encompasses. The larger patch is then sub-divided into any covered smaller patches, and the process repeated. The rasterizer also identifies when a given smaller patch of the render output is found to entirely pass the edge test for an edge of the primitive in question when the larger patch encompassing that smaller patch is tested, notes that event in state information associated with the primitive edge in question, and then uses that state information to skip the testing of the edge in question against the smaller patch of the render output.