Abstract: An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

Abstract: A multi-chip package structure is provided. The multi-chip package structure includes a first IC chip and a second IC chip, and a fluid conduit thermally coupled to the first IC chip and the second IC chip. The multi-chip package structure is configured to remove heat generated by at least one of the first IC chip and the second IC chip. The fluid conduit has a first end and a second end opposite to the first end. The multi-chip package structure also includes a first monopole feed connected between the first IC chip and the first end of the fluid conduit, and a second monopole feed connected between the second IC chip and the second end of the fluid conduit. The first monopole feed is configured to transmit an electromagnetic signal through the fluid conduit toward the second monopole feed and vice versa.

Abstract: Methods and apparatuses for vertically transitioning signals between substrate integrated waveguides within a multilayered printed circuit board (PCB) are disclosed. A first substrate integrated waveguide (SIW) is provided in a first layer of the PCB, the first SIW having a first terminal portion. A second SIW is provided in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion, wherein a first ground plane separates the first SIW and the second SIW. A vertical transition comprising an aperture in the first ground plane that is disposed in an area defined by the overlap of the first terminal portion and the second terminal portion, such that a signal propagated in the first SIW transitions to the second SIW in a different layer through the aperture.

Abstract: A printed circuit board (‘PCB’) including a substrate integrated waveguide (‘SIW’) formed using two ground planes representing the top and bottom walls of the waveguide, tightly pitched ground vias to act as two side walls and two back walls, and a pair of monopole antennas placed at each end of the SIW acting as signal feeding/receiving structures is disclosed. The waveguide dominant mode cut off frequency is determined by the spacing between the two side walls. Within each monopole antenna pair, the first monopole antenna operates at a first frequency while the second monopole antenna operates at another frequency. For each monopole antenna pair, the first monopole antenna and the second monopole antenna are located in the SIW at a distance from the back wall optimal for each operating frequency.

Abstract: A printed circuit board (‘PCB’) including a substrate integrated waveguide (‘SIW’) formed using two ground planes representing the top and bottom walls of the waveguide, tightly pitched ground vias to act as two side walls and two back walls, and a pair of monopole antennas placed at each end of the SIW acting as signal feeding/receiving structures is disclosed. The waveguide dominant mode cut off frequency is determined by the spacing between the two side walls. Within each monopole antenna pair, the first monopole antenna operates at a first frequency while the second monopole antenna operates at another frequency. For each monopole antenna pair, the first monopole antenna and the second monopole antenna are located in the SIW at a distance from the back wall optimal for each operating frequency.

Abstract: Methods and apparatuses for vertically transitioning signals between substrate integrated waveguides within a multilayered printed circuit board (PCB) are disclosed. A first substrate integrated waveguide (SIW) is provided in a first layer of the PCB, the first SIW having a first terminal portion. A second SIW is provided in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion, wherein a first ground plane separates the first SIW and the second SIW. A vertical transition comprising an aperture in the first ground plane that is disposed in an area defined by the overlap of the first terminal portion and the second terminal portion, such that a signal propagated in the first SIW transitions to the second SIW in a different layer through the aperture.

Abstract: A method and apparatus for attenuating crosstalk between dielectric waveguides is provided. A first dielectric waveguide is formed to carry a first frequency band. A first filter is embedded within the first dielectric waveguide to attenuate transmission of a second frequency band through the first dielectric waveguide. The filter comprises alternating sections of a first dielectric material and a second dielectric material having different dielectric constants. The length of each section of the first and second dielectric materials is equal to a quarter of the wavelength of the central frequency of the second frequency band. A second waveguide is formed to carry the second frequency band. A second filter is embedded in the second dielectric waveguide to attenuate transmission of the first frequency band through the second dielectric waveguide. A cladding is disposed between the first and second waveguides.

Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.

Abstract: A method and apparatus for attenuating crosstalk between dielectric waveguides is provided. A first dielectric waveguide is formed to carry a first frequency band. A first filter is embedded within the first dielectric waveguide to attenuate transmission of a second frequency band through the first dielectric waveguide. The filter comprises alternating sections of a first dielectric material and a second dielectric material having different dielectric constants. The length of each section of the first and second dielectric materials is equal to a quarter of the wavelength of the central frequency of the second frequency band. A second waveguide is formed to carry the second frequency band. A second filter is embedded in the second dielectric waveguide to attenuate transmission of the first frequency band through the second dielectric waveguide. A cladding is disposed between the first and second waveguides.

Abstract: Embodiments herein describe a high-speed communication channel in a PCB that includes a dielectric waveguide sandwiched between two ground layers. The dielectric waveguide includes a core and a cladding where the material of the core has a higher dielectric constant than the material of the cladding. Thus, electromagnetic signals propagating in the core are internally reflected at the interface between the core and cladding such that the electromagnetic signals are primary contained in the core.

Abstract: Embodiments herein describe a high-speed communication channel in a PCB that includes a dielectric waveguide sandwiched between two ground layers. The dielectric waveguide includes a core and a cladding where the material of the core has a higher dielectric constant than the material of the cladding. Thus, electromagnetic signals propagating in the core are internally reflected at the interface between the core and cladding such that the electromagnetic signals are primary contained in the core.

Abstract: Disclosed aspects relate to cooling electronics. A set of recirculation flaps is coupled with a cooling fan. At least one recirculation flap has a ferrous material. In various embodiments, the set of recirculation flaps is arranged in an open position in response to air pressure from the cooling fan, and is arranged in a closed position in response to substantially no air pressure from the cooling fan. A controller is coupled with the cooling fan. The controller indicates a set of indicated positions for the set of recirculation flaps based on a tachometer value. An electromagnet is connected with the controller to position the set of recirculation flaps in the set of indicated positions using the ferrous material. In various embodiments, the electromagnet engages the ferrous material to arrange the set of recirculation flaps in an open position.

Abstract: Disclosed aspects relate to cooling electronics. A set of recirculation flaps is coupled with a cooling fan. At least one recirculation flap has a ferrous material. In various embodiments, the set of recirculation flaps is arranged in an open position in response to air pressure from the cooling fan, and is arranged in a closed position in response to substantially no air pressure from the cooling fan. A controller is coupled with the cooling fan. The controller indicates a set of indicated positions for the set of recirculation flaps based on a tachometer value. An electromagnet is connected with the controller to position the set of recirculation flaps in the set of indicated positions using the ferrous material. In various embodiments, the electromagnet engages the ferrous material to arrange the set of recirculation flaps in an open position.

Abstract: Embodiments herein describe a high-speed communication channel in a PCB that includes a dielectric waveguide coupled at respective ends to coaxial vias. The dielectric waveguide includes a core and a cladding where the material of the core has a higher dielectric constant than the material of the cladding. Thus, electromagnetic signals propagating in the core are internally reflected at the interface between the core and cladding such that the electromagnetic signals are primary contained in the core. The coaxial vias include a center conductor and an outer conductor (or shield) which extend through one or more layers of the PCB. One of the coaxial vias radiates electromagnetic signals into the dielectric waveguide at a first end of the core while the other coaxial via receives the radiated signals at a second end of the core.

Abstract: Embodiments of the present invention include a method for fabricating a hybrid land grid array connector and the resulting structures. A body is provided. The body includes a first plurality of holes and a second plurality of holes. A conductive layer is deposited on the top and bottom surfaces of the body and the wall surfaces of the first plurality of holes resulting in the top and bottom surfaces being electrically common. The conductive layer is removed from the wall surfaces of a first subset of the first plurality of holes. A portion of the conductive layer is removed from the top surface of the body and the bottom surface of the body from an area surrounding the first subset of the first plurality of holes.

Abstract: Embodiments of the present invention include a method for fabricating a hybrid land grid array connector and the resulting structures. A body is provided. The body includes a first plurality of holes and a second plurality of holes. A conductive layer is deposited on the top and bottom surfaces of the body and the wall surfaces of the first plurality of holes resulting in the top and bottom surfaces being electrically common. The conductive layer is removed from the wall surfaces of a first subset of the first plurality of holes. A portion of the conductive layer is removed from the top surface of the body and the bottom surface of the body from an area surrounding the first subset of the first plurality of holes.

Abstract: A process of forming an angled fiberglass cloth weave includes weaving a first set of fibers oriented at a first non-orthogonal angle with respect to a printed circuit board to be formed from the angled fiberglass cloth weave with a second set of fibers oriented at a second non-orthogonal angle with respect to the printed circuit board to be formed form the angled fiberglass cloth weave.

Abstract: Embodiments herein describe a high-speed communication channel in a PCB that includes a dielectric waveguide sandwiched between two ground layers. The dielectric waveguide includes a core and a cladding where the material of the core has a higher dielectric constant than the material of the cladding. Thus, electromagnetic signals propagating in the core are internally reflected at the interface between the core and cladding such that the electromagnetic signals are primary contained in the core.

Abstract: Embodiments herein describe a high-speed communication channel in a PCB that includes a dielectric waveguide sandwiched between two ground layers. The dielectric waveguide includes a core and a cladding where the material of the core has a higher dielectric constant than the material of the cladding. Thus, electromagnetic signals propagating in the core are internally reflected at the interface between the core and cladding such that the electromagnetic signals are primary contained in the core.

Abstract: Mechanisms are provided for implementing a skew rate artificial neural network (ANN). The mechanisms generate a training dataset for training the skew rate ANN. The training dataset comprises a plurality of sets of data and each set of data corresponds to a particular set of printed circuit board (PCB) and communication channel characteristics. The mechanisms train the skew rate ANN based on the training dataset to generate a trained skew rate ANN. The mechanisms then receive an input dataset representing a set of PCB and communication channel characteristics for a PCB design. The trained skew rate ANN generates a predicted skew factor for the PCB design based on the input dataset. The predicted skew factor is then output to a PCB design tool to modify the PCB design based on the predicted skew factor.