Patents by Inventor Jose Fridman
Jose Fridman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9639356Abstract: An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.Type: GrantFiled: March 15, 2013Date of Patent: May 2, 2017Assignee: Qualcomm IncorporatedInventors: Marc M. Hoffman, Ajay Anant Ingle, Jose Fridman
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Patent number: 9632781Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.Type: GrantFiled: February 26, 2013Date of Patent: April 25, 2017Assignee: QUALCOMM IncorporatedInventors: Ajay A. Ingle, Marc M. Hoffman, Jose Fridman, Lucian Codrescu
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Patent number: 9363749Abstract: A system and method dynamically scale power consumed by the circuitry of an electronic device based on channel state and/or data rate. The electronic device then operates according to the power scaling. The scaling may be in accordance with an effective data rate, a number of multiple input multiple output (MIMO) layers, receiver type, a cell scenario, or a number of carriers. A number of MIMO layers can be predicted based on at least one of channel conditions or a channel quality index (CQI).Type: GrantFiled: August 15, 2013Date of Patent: June 7, 2016Assignee: QUALCOMM INCORPORATEDInventors: Deepak Mathew, Garret Webster Shih, Jose Fridman, Robin Lee Brown
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Patent number: 9342479Abstract: Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.Type: GrantFiled: August 23, 2012Date of Patent: May 17, 2016Assignee: QUALCOMM IncorporatedInventors: Jose Fridman, Ajay Anant Ingle, Deepak Mathew, Marc M. Hoffman, Michael John Lopez
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Publication number: 20140281368Abstract: An example method for executing multiple instructions in one or more slots includes receiving a packet including multiple instructions and executing the multiple instructions in one or more slots in a time shared manner. Each slot is associated with an execution data path or a memory data path. An example method for executing at least one instruction in a plurality of phases includes receiving a packet including an instruction, splitting the instruction into a plurality of phases, and executing the instruction in the plurality of phases.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: QUALCOMM INCORPORATEDInventors: Ajay Anant Ingle, Lucian Codrescu, David J. Hoyle, Jose Fridman, Marc M. Hoffman, Deepak Mathew
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Publication number: 20140281421Abstract: An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: QUALCOMM INCORPORATEDInventors: Marc M. Hoffman, Ajay Anant Ingle, Jose Fridman
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Publication number: 20140258680Abstract: Techniques are addressed for parallel dispatch of coprocessor and thread instructions to a coprocessor coupled to a threaded processor. A first packet of threaded processor instructions is accessed from an instruction fetch queue (IFQ) and a second packet of coprocessor instructions is accessed from the IFQ. The IFQ includes a plurality of thread queues that are each configured to store instructions associated with a specific thread of instructions. A dispatch circuit is configured to select the first packet of thread instructions from the IFQ and the second packet of coprocessor instructions from the IFQ and send the first packet to a threaded processor and the second packet to the coprocessor in parallel. A data port is configured to share data between the coprocessor and a register file in the threaded processor. Data port operations are accomplished without affecting operations on any thread executing on the threaded processor.Type: ApplicationFiled: March 5, 2013Publication date: September 11, 2014Applicant: QUALCOMM INCORPORATEDInventors: Ajay Anant Ingle, Lucian Codrescu, Suresh K. Venkumahanti, Jose Fridman
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Publication number: 20140244967Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified, in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.Type: ApplicationFiled: February 26, 2013Publication date: August 28, 2014Applicant: Qualcomm IncorporatedInventors: Ajay A. Ingle, Marc M. Hoffman, Jose Fridman, Lucian Codrescu
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Patent number: 8804844Abstract: Images are obtained for image compression. The images are compared using sum of absolute difference devices, which have arithmetic parts, and accumulators. The sign bits of the accumulators are determined at a time of minimum distortion between two images. These sign bits are associated with sets of probabilistically-similar parts. When other sets from that set are obtained later, an early exit is established.Type: GrantFiled: May 25, 2005Date of Patent: August 12, 2014Assignee: Analog Devices, Inc.Inventors: Bradley C. Aldrich, Jose Fridman
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Publication number: 20140071869Abstract: A system and method dynamically scale power consumed by the circuitry of an electronic device based on channel state and/or data rate. The electronic device then operates according to the power scaling. The scaling may be in accordance with an effective data rate, a number of multiple input multiple output (MIMO) layers, receiver type, a cell scenario, or a number of carriers. A number of MIMO layers can be predicted based on at least one of channel conditions or a channel quality index (CQI).Type: ApplicationFiled: August 15, 2013Publication date: March 13, 2014Applicant: QUALCOMM IncorporatedInventors: Deepak MATHEW, Garret Webster SHIH, Jose FRIDMAN, Robin L. BROWN
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Publication number: 20140059323Abstract: Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.Type: ApplicationFiled: August 23, 2012Publication date: February 27, 2014Applicant: Qualcomm IncorporatedInventors: Jose Fridman, Ajay Anant Ingle, Deepak Mathew, Marc M. Hoffman, Michael John Lopez
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Patent number: 7333530Abstract: A digital signal processor performs despread decoding in wireless telephone systems. Orthogonal codes are used to combine data signals into one overall coded signal which is transmitted. The orthogonal codes are used to retrieve individual data signals from the transmitted overall coded signal. Despread instructions are included in the digital signal processor functionality.Type: GrantFiled: August 6, 2001Date of Patent: February 19, 2008Assignee: Analog Devices, Inc.Inventors: Rasekh Rifaat, Zvi Greenfield, Jose Fridman
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Patent number: 7154950Abstract: Plural sum of absolute difference devices are used to calculate distortions between specified parts of specified images in a video stream. The video can be from a video camera, or other device.Type: GrantFiled: November 24, 2003Date of Patent: December 26, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Bradley C. Aldrich, Jose Fridman
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Patent number: 7111155Abstract: A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.Type: GrantFiled: May 12, 2000Date of Patent: September 19, 2006Assignee: Analog Devices, Inc.Inventors: William C. Anderson, John Edmondson, Jose Fridman, Marc Hoffman, Russell L. Rivin
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Patent number: 7107302Abstract: A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.Type: GrantFiled: May 12, 2000Date of Patent: September 12, 2006Assignee: Analog Devices, Inc.Inventors: Jose Fridman, Marc Hoffman
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Patent number: 7062523Abstract: A method for computing an out of place FFT in which each stage of the FFT has an identical signal flow geometry. In each stage of the presently disclosed FFT method the group loop has been eliminated, the twiddle factor data is stored in bit-reversed manner, and the output data values are stored with a unity stride.Type: GrantFiled: August 1, 2000Date of Patent: June 13, 2006Assignee: Analog Devices, Inc.Inventors: Marc Hoffman, Jose Fridman
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Patent number: 7047271Abstract: In one embodiment, a digital signal processor (DSP) processes both n-bit data and (n/2)-bit data. The DSP includes multiple processing paths. A first processing path processes n-bit data. A second processing path is processes (n/2)-bit data. The multiple processing paths may be established using multiple components or may share components. When the processing paths share components, only one of the processing paths may be used at a time.Type: GrantFiled: April 20, 2004Date of Patent: May 16, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Bradley C. Aldrich, Jose Fridman, Paul Meyer, Gang Liang
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Publication number: 20060101230Abstract: In one embodiment, a programmable processor searches an array of N data elements in response to N/M machine instructions, where the processor has a pipeline configured to process M data elements in parallel. In response to the machine instructions, a control unit directs the pipeline to retrieve M data elements from the array of elements in a single fetch cycle, concurrently compare the data elements to M current extreme values, and update the current extreme values, as well as M references to the current extreme values, based on the comparisons.Type: ApplicationFiled: September 20, 2005Publication date: May 11, 2006Inventors: Charles Roth, Ravi Kolagotla, Jose Fridman
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Patent number: 7043582Abstract: A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may be deferred until the ISR for a subsequently received interrupt of the same priority level is completed.Type: GrantFiled: September 6, 2002Date of Patent: May 9, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Ravi P. Singh, Thomas Tomazin, Charles P. Roth, Jose Fridman, Michael Allen
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Patent number: 7031498Abstract: An image processor that calculates values that are related to distortion between two image parts. The values are detected in a previous calculation. Those values are then used in the next calculation cycle to detect an early exit. That value, called least, divided by the number of accumulators, and its negative is loaded into the accumulators. When the accumulators reach zero, an early exit is established.Type: GrantFiled: February 9, 2004Date of Patent: April 18, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Bradley C. Aldrich, Jose Fridman