Abstract: An aerial imaging system and method of aerially capturing an image including a first unmanned aerial vehicle (UAV) and a second UAV. The first UAV includes a camera and may be configured to receive input from an operator. The second UAV may be configured to dock with and deploy from the first UAV. The second UAV includes a light configured to provide remote illumination for the camera. The light on the second UAV may be activated to illuminate a target of photography by the camera while the second UAV is flown separate from the first UAV.

Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol.

Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol.

Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

Abstract: An automatic frequency control circuit (84) and a method for automatic frequency control in a digital receiver includes a CORDIC vector rotation processor (88), an FM demodulator (100) and an integrator (72). The circuit and method utilize the CORDIC computing technique to simplify required circuitry and to reduce required software processing power over conventional automatic frequency control techniques.

Abstract: A circuit (10) for determining a radius value and a phase value from an in-phase signal I(n) and a quadrature signal Q(n) iteratively approximates the phase value and the radius value based upon initial in-phase signal and quadrature signal preferably using the coordinate rotational digital computer (CORDIC) algorithm. The circuit (10) includes a multi-task arithmetic unit (50), memory (20), and a controller (30). The multi-task arithmetic unit includes registers (12, 14, 16), multiplexers (18, 22), shift registers (24, 25), and an adder (26) to perform various arithmetic operations. The circuit (10) further includes dynamic memory (32) for storing the solutions at different points in time of the radius value and phase value, which are subsequently used in the filtering of radius values and phase values.

Abstract: An integrated circuit that provides multiple communication functions is accomplished by providing an integrated circuit (24) that includes memory (70) which stores an audio code algorithm, echo cancellation information, a modem processing algorithm, and audio data. The memory (70) is coupled via a data bus (50) to a signal converter (56), a central processing unit (58), and a first co-processor (72). The signal converter (56) provides an analog-to-digital input port (78) and a digital-to-analog output port (80) for the integrated circuit (24), wherein the audio data is received via the analog-to-digital input port (78). The central processing unit (58) executes at least a first portion of the audio coding algorithm upon the audio data and executes a first portion of the modem processing algorithm, while the first co-processor (72) executes an echo cancellation algorithm.

Abstract: An ADPCM transcoder (60) includes an integral tone generator (65) which inserts a linear tone signal, such as a conventional DTMF tone signal, into either the transmit or receive data stream, or both. A digital PCM input signal is first converted to a first linear signal. If tone generation is enabled for transmission, then the linear tone signal is substituted for or added to the first linear signal and provided to an ADPCM encoder (63), which provides an ADPCM output signal in response. An ADPCM decoder (66) receives an ADPCM input signal and provides a second linear input signal in response. If tone generation is enabled for reception, then the linear tone signal is substituted for or added to the second linear input signal, and converted to a digital PCM output signal. The ADPCM transcoder (60) may also be integrated with other components of a signal processing system.

Abstract: A signal processor such as an ADPCM decoder (28b) receives an input signal. As part of the CCITT Recommendation G.726 algorithm, ADPCM decoder (28b) processes the input signal to provide a linear reconstructed signal s.sub.r (k). When enabled, a noise detector (50) samples the reconstructed signal s.sub.r (k) once for each of a predetermined number of received samples. The noise detector (50) adds the absolute value of the reconstructed signal s.sub.r (k) to a total energy estimate. At the end of the predetermined number of samples, the noise detector (50) compares the total energy estimate to a product of a noise threshold and the predetermined number. If the total energy estimate exceeds this product, then a noise indication is provided. This calculation prevents the need for time-consuming division operation which is difficult for high-performance digital signal processors (70).

Abstract: A signal processor such as an ADPCM decoder (128b) receives an input signal. As part of the CCITT Recommendation G.726 algorithm, an inverse adaptive quantizer (41) processes the input signal to provide a quantized difference signal d.sub.q (k). When enabled, a noise detector (50) samples signal d.sub.q (k) once for each of a predetermined number of received samples. The noise detector (50) adds the absolute value of signal d.sub.q (k) to a total energy estimate. At the end of the predetermined number of samples, the noise detector (50) compares the total energy estimate to a product of a noise threshold and the predetermined number. If the total energy estimate exceeds this product, then a noise indication is provided. In another embodiment (228b) a noise detector (250) compares an existing energy estimate signal d.sub.ml (k) computed by an adaptation speed control block (48) as part of the G.726 algorithm to an energy threshold to save processing time.

Abstract: An integral digital receive gain (44) for a G.721 or G.726 ADPCM decoder (28a) or the like in an application such as a CT-2 handset (20) allows digital volume control without the need for external components. The digital receive gain (44) receives a reconstructed signal s.sub.r (k) and a variable gain factor. The integral digital receive gain (44) multiplies the reconstructed signal by the gain factor and provides the result as an input to an output PCM format conversion (45). The digital receive gain (44) also disables a synchronous coding adjustment (46) if a gain setting other than unity gain is detected.

Abstract: A data processing system uses the same structure and hardware to implement either a general purpose multiplier or arithmetic operations associated with the least-mean-squares (LMS) algorithm. Multiplier and adder circuits are time-shared to perform the myriad functions. In one form, further modified Booth's algorithm is utilized so that an output product of two binary input numbers may be quickly formed by executing a series of multiplications and accumulations. The operation is pipelined for continuous processing activity.