Patents by Inventor Jose Jehrome RANDO
Jose Jehrome RANDO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10403362Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.Type: GrantFiled: January 23, 2019Date of Patent: September 3, 2019Assignee: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Patent number: 10384449Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.Type: GrantFiled: March 2, 2018Date of Patent: August 20, 2019Assignee: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Jose Jehrome Rando
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Publication number: 20190156892Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.Type: ApplicationFiled: January 23, 2019Publication date: May 23, 2019Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Patent number: 10236063Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.Type: GrantFiled: May 22, 2018Date of Patent: March 19, 2019Assignee: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Patent number: 10084062Abstract: In some examples, a semiconductor device includes a substrate, a first doped region formed in the substrate, a second doped region around and spaced apart from the first doped region, and a channel between the first and second doped regions and formed using a gate ring on the substrate as a mask. A gate is formed over only a portion of the channel, the gate being a portion of the gate ring.Type: GrantFiled: July 24, 2017Date of Patent: September 25, 2018Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Ning Ge, Leong Yap Chia, Pin Chin Lee, Jose Jehrome Rando
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Publication number: 20180268905Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.Type: ApplicationFiled: May 22, 2018Publication date: September 20, 2018Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Patent number: 10029457Abstract: A nozzle firing cell may comprise a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge line and a gate of the firing transistor wherein the pre-charge line is routed over the gate of the pre-charge transistor. A fluid ejection device may comprise a circuit comprising a nozzle firing cell, the nozzle firing cell comprising a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge Sine and a gate of the firing transistor in which the pre-charge line is routed over the gate of the pre-charge transistor. A circuit may comprise a number of firing transistors and a number of pre-charge transistors each having a source and drain coupled between a pre-charge line and a gate of one of the firing transistors in which the pre-charge line is routed over each of the gates of the pre-charge transistors.Type: GrantFiled: July 30, 2014Date of Patent: July 24, 2018Assignee: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Publication number: 20180186151Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.Type: ApplicationFiled: March 2, 2018Publication date: July 5, 2018Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Jose Jehrome Rando
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Patent number: 10014055Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.Type: GrantFiled: July 30, 2014Date of Patent: July 3, 2018Assignee: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Patent number: 9975335Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.Type: GrantFiled: August 18, 2014Date of Patent: May 22, 2018Assignee: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Jose Jehrome Rando
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Patent number: 9953991Abstract: An electronically programmable read-only memory (EPROM) cell includes a semiconductor substrate having source and drain regions; a floating gate, adjacent to the source and drain regions and separated from the semiconductor substrate by a first dielectric layer, the floating gate including: a polysilicon layer formed over the first dielectric layer; a first metal layer electrically connected to the polysilicon layer, where the surface area of the first metal layer is less than 1000 ?m2; and a control gate comprising a second metal layer, capacitively coupled to the first metal layer through a second dielectric material disposed therebetween.Type: GrantFiled: March 14, 2014Date of Patent: April 24, 2018Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ning Ge, Leong Yap Chia, Jose Jehrome Rando
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Publication number: 20170323961Abstract: In some examples, a semiconductor device includes a substrate, a first doped region formed in the substrate, a second doped region around and spaced apart from the first doped region, and a channel between the first and second doped regions and formed using a gate ring on the substrate as a mask. A gate is formed over only a portion of the channel, the gate being a portion of the gate ring.Type: ApplicationFiled: July 24, 2017Publication date: November 9, 2017Inventors: Ning GE, Leong Yap CHIA, Pin Chin LEE, Jose Jehrome RANDO
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Patent number: 9786777Abstract: A semiconductor device and method of forming the same is described. In an example, a polysilicon layer is deposited on a substrate having at least one polysilicon ring. The substrate is doped using the polysilicon layer as a mask to form doped regions in the substrate. A dielectric layer is deposited over the polysilicon layer and the substrate. The dielectric layer is etched to expose portions of the polysilicon layer. A metal layer is deposited on the dielectric layer. The metal layer, the dielectric layer, and the exposed portions of the polysilicon layer are etched such that at least a portion of each polysilicon ring is removed.Type: GrantFiled: August 30, 2013Date of Patent: October 10, 2017Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Ning Ge, Leong Yap Chia, Pin Chin Lee, Jose Jehrome Rando
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Publication number: 20170225462Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.Type: ApplicationFiled: August 18, 2014Publication date: August 10, 2017Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Jose Jehrome Rando
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Publication number: 20170210124Abstract: A nozzle firing cell may comprise a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge line and a gate of the firing transistor wherein the pre-charge line is routed over the gate of the pre-charge transistor. A fluid ejection device may comprise a circuit comprising a nozzle firing ceil, the nozzle firing cell comprising a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge Sine and a gate of the firing transistor in which the pre-charge line is routed over the gate of the pre-charge transistor. A circuit may comprise a number of firing transistors and a number of pre-charge transistors each having a source and drain coupled between a pre-charge line and a gate of one of the firing transistors in which the pre-charge line is routed over each of the gates of the pre-charge transistors.Type: ApplicationFiled: July 30, 2014Publication date: July 27, 2017Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Publication number: 20170213596Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.Type: ApplicationFiled: July 30, 2014Publication date: July 27, 2017Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Publication number: 20170069639Abstract: An electronically programmable read-only memory (EPROM) cell includes a semiconductor substrate having source and drain regions; a floating gate, adjacent to the source and drain regions and separated from the semiconductor substrate by a first dielectric layer, the floating gate including: a polysilicon layer formed over the first dielectric layer; a first metal layer electrically connected to the polysilicon layer, where the surface area of the first metal layer is less than 1000 ?m2; and a control gate comprising a second metal layer, capacitively coupled to the first metal layer through a second dielectric material disposed therebetween.Type: ApplicationFiled: March 14, 2014Publication date: March 9, 2017Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Ning GE, Leong Yap CHIA, Jose Jehrome Rando
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Publication number: 20160204244Abstract: A semiconductor device and method of forming the same is described. In an example, a polysilicon layer is deposited on a substrate having at least one polysilicon ring. The substrate is doped using the polysilicon layer as a mask to form doped regions in the substrate. A dielectric layer is deposited over the polysilicon layer and the substrate. The dielectric layer is etched to expose portions of the polysilicon layer. A metal layer is deposited on the dielectric layer. The metal layer, the dielectric layer, and the exposed portions of the polysilicon layer are etched such that at least a portion of each polysilicon ring is removed.Type: ApplicationFiled: August 30, 2013Publication date: July 14, 2016Inventors: Ning GE, Leong Yap CHIA, Pin Chin LEE, Jose Jehrome RANDO