Abstract: Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for process driver designs which may not have enough data on process characteristics. This invention allows us to recoup these inefficiencies and to speed up the power up/power down dynamically. This invention sequences plural power supply switches serially or in plural parallel sets as set by a wake up mode.

Abstract: This invention makes the change in current drawn from the power grid in an integrated circuit gradual by sequencing the power switch chains differently for both power up and power down. During power up, this invention establishes a reasonable connection with the power grid through a series of weak power switches and then starts turning on the strong power switches. During power down, this invention reverses the process. Strong switches are all turned off before turning off the weak switches.

Abstract: Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for process driver designs which may not have enough data on process characteristics. This invention allows us to recoup these inefficiencies and to speed up the power up/power down dynamically. This invention sequences plural power supply switches serially or in plural parallel sets as set by a wake up mode.

Abstract: This invention places plural ring oscillators on a semiconductor chip during manufacture. The respective oscillation frequencies of these ring oscillators are measured. The semiconductor chip is assigned a grade dependent upon the measured frequencies. The ring oscillators are disposed proximate to critical paths on the semiconductor chip and employ circuit types to model the critical path operation under as many the manufacturing variations as possible. A linearly fitted model of ring oscillator frequencies to critical path delays is constructed during characterization after manufacture.

Abstract: An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.

Abstract: An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: This invention places plural ring oscillators on a semiconductor chip during manufacture. The respective oscillation frequencies of these ring oscillators are measured. The semiconductor chip is assigned a grade dependent upon the measured frequencies. The ring oscillators are disposed proximate to critical paths on the semiconductor chip and employ circuit types to model the critical path operation under as many the manufacturing variations as possible. A linearly fitted model of ring oscillator frequencies to critical path delays is constructed during characterization after manufacture.

Abstract: An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.

Abstract: An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: A method and apparatus for trace data alignment for trace data generated during differing instruction pipeline stages selectively delays write data, memory access address and memory access control data zero, one or two pipeline stages dependent upon the memory access control data. Program counter data delayed by one clock cycle is delayed one pipeline stage if the next instruction is a new instruction. Program counter control data is also delayed one pipeline stage. The write data, memory access address, memory access control data, program counter data and program counter control data are further delayed a number of pipeline stages to align with read data. The program counter data holds if the pipeline is stalled. The write data, memory access address, memory access control data, program counter data and program counter control data holds in the multistage pipeline delay register if the pipeline is stalled.

Abstract: Trace data is aligned in a processor having an instruction pipeline by delaying write data and read data a predetermined number of clock cycles, selectively swapping both most significant write data and read data with least significant write data and read dependent upon memory access control data. The write and read data pass normally for even memory bank accesses and are swapped for odd memory bank accesses. Memory access control data, program counter data and program counter control data are similarly delayed. At least the read data and optionally all the data are held upon a pipeline stall.

Abstract: Trace data is aligned in a processor having an instruction pipeline by delaying write data and read data a predetermined number of clock cycles, selectively swapping both most significant write data and read data with least significant write data and read dependent upon memory access control data. The write and read data pass normally for even memory bank accesses and are swapped for odd memory bank accesses. Memory access control data, program counter data and program counter control data are similarly delayed. At least the read data and optionally all the data are held upon a pipeline stall.

Abstract: An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: A method and apparatus for trace data alignment for trace data generated during differing instruction pipeline stages selectively delays write data, memory access address and memory access control data zero, one or two pipeline stages dependent upon the memory access control data. Program counter data delayed by one clock cycle is delayed one pipeline stage if the next instruction is a new instruction. Program counter control data is also delayed one pipeline stage. The write data, memory access address, memory access control data, program counter data and program counter control data are further delayed a number of pipeline stages to align with read data. The program counter data holds if the pipeline is stalled. The write data, memory access address, memory access control data, program counter data and program counter control data holds in the multistage pipeline delay register if the pipeline is stalled.

Abstract: An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.

Abstract: Systems and methods are described for guaranteeing the availability of per thread storage in a distributed computing environment.

Abstract: A lubricating device for machine shafts applicable to mechanisms having a solid shaft with a central portion of less diameter than two flanking portions. The flanking portions are threaded in precisely opposite directions for transferring lubricating fluid to bearings supporting the solid shaft and a hollow shaft, the hollow shaft being externally and coaxially disposed with respect to the solid shaft. The hollow shaft has a plurality of holes for allowing the circulation of lubricating fluid. The device includes an obturator-slinger component for restricting and changing the direction of oil flow and for slinging lubricating fluid from a chamber located adjacent a bearing supporting the solid shaft.