Abstract: Machine learning is a process that learns a neural network model from a given dataset, where the model can then be used to make a prediction about new data. In order to reduce the size, computation, and latency of a neural network model, a compression technique can be employed which includes model sparsification. To avoid the negative consequences of pruning a fully pretrained neural network model and on the other hand of training a sparse model in the first place without any recovery option, the present disclosure provides a dynamic neural network model sparsification process which allows for recovery of previously pruned parts to improve the quality of the sparse neural network model.

Abstract: A device (10) for detecting highly energetic photons, comprising one or more pixelated solid-state detectors (11) for detecting the highly energetic photons; means for providing a high voltage for polarizing said solid-state detectors; one or more pixelated readout elements (30), a readout element being connected to each of said one or more pixelated solid-state detectors (11); an input/output element (12) connected to said readout elements (30) for data input and output; and a base layer (13) for mounting the pixelated solid-state detectors (11), the readout elements (30) and the input/output element (12).

Abstract: A device (10) for detecting highly energetic photons, comprising one or more pixelated solid-state detectors (11) for detecting the highly energetic photons; means for providing a high voltage for polarizing said solid-state detectors; one or more pixelated readout elements (30), a readout element being connected to each of said one or more pixelated solid-state detectors (11); an input/output element (12) connected to said readout elements (30) for data input and output; and a base layer (13) for mounting the pixelated solid-state detectors (11), the readout elements (30) and the input/output element (12).

Abstract: An output buffer translates digital input signals which toggle between ground and V.sub.DDL to signals which toggle between ground and V.sub.DDH. The technology dielectric breakdown voltage limit is less than the magnitude of V.sub.DDH, such that use of a traditional output stage would subject transistors' dielectrics to voltages which exceed their dielectric breakdown limit, and would thus be damaged. Predrive circuits (40, 50) control output stage (70) transistors' (72, 78) gates, and voltage dropping circuits control output stage (70) transistors (74, 76). These control signals are generated specifically to maximize output stage transistor drive strengths, thereby minimizing output stage size. Output buffer functions when V.sub.DDL =V.sub.DDH, and its performance is V.sub.DDL independent. Temperature compensation is incorporated into the output buffer by deliberately offsetting temperature effects on output stage transistor drive strengths.

Abstract: A method and apparatus are provided for generating a phase-controlled clock signal within a microprocessor. A first clock signal having a first frequency is input. After a reset event, the first clock signal transitions in a first direction at a time t. A second clock signal is output having a second frequency related to the first frequency by a non-integer ratio. The second clock signal transitions in the same direction as the first clock signal at time t.

Abstract: The mechanical damper is fabricated from a relatively thin metal spring stock and formed in cross-section to an E-shape that is arcuately bent into a ring that fits into the cavity defined between the inner diameter of the inner shroud and the outer diameter of the segmented back rings of the honeycomb sealing structure of the stator for the compressor of a gas turbine engine. The E-shaped damper is segmented and provides damping of the compressor stator of a gas turbine engine and is particularly adapted for stators that are formed from integrally cast stator vanes and shrouds.