Abstract: The invention relates to a signalling method using orthogonal frequency division multiplexing (OFDM), based on a preamble comprising N dedicated carriers (frequency pilots), the position and modulation of which is defined by one or more concatenated complementary sequences of length N. Complementary sequences are those for which the sum of the autocorrelations thereof is zero except for zero shift, i.e. a Krönecker delta. The main purpose of said preamble is to signal the basic properties of the transmitted signal and to provide a first estimation at the moment of time and frequency synchronisation. The preamble is multiplexed or sequenced temporally with the transmitted data using OFDM prior to the application of the inverse Fourier transform by the inverse fast Fourier transform (IFFT) block.

Abstract: The invention relates to a method and system for multiple input and multiple output channel estimation, which can be used to generate and correlate sets of complementary sequences of length N, having a number of elements K greater than or equal to two. According to the invention, a block is used to generate sequences and to convolve same with an input signal, after which they are sent directly, or modulated, to the transmission channel. Once they have been received, and optionally demodulated, they pass through a correlator filter such as to obtain the input signal convolved by the channel, having a noise level reduced by factor KN.

Abstract: A user-programmable integrated circuit that includes over the same silicon die a) a set of programmable logic cells such as the ones used in already reported FPGAs; b) a set of programmable mixed signal and analog cells, in particular the necessary circuitry for signal conditioning acquisition and generation, such as operational amplifiers, filters, comparators, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs); c) a microprocessor used both for controlling and configuring the whole system and for running general purpose user programs; and d) optimized interfaces between these three blocks that would allow the user to read the digital signals implemented in the programmable logic array as memory locations in real time, directly interface the digital part of the analog and digital signals from the microprocessor and from the programmable logic, and configure and dynamically reconfigure all the programmable features of the system with the microprocessor, between countless other possibi