Patents by Inventor Jose Tellado

Jose Tellado has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7720015
    Abstract: A device and method for a full-duplex transceiver is disclosed. The transceiver includes a transmitter DAC coupled to a transmission channel. The transmit DAC converting a digital transmission signal into an analog transmission signal. The transceiver further includes a receiver connected to the transmission channel. The receiver receives a desired signal and an echo signal, in which the echo signal includes at least a portion of the analog transmission signal. The receiver includes a receiver ADC, a programmable delay line for adjustably delaying a clock signal of the ADC, and a receiver processing circuit for adjusting the delay of the clock signal based at least in part upon the echo signal.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: May 18, 2010
    Assignee: Teranetics, Inc.
    Inventors: Sandeep Kumar Gupta, Jose Tellado
  • Publication number: 20100104056
    Abstract: An apparatus and method of controlling activation of electronic circuitry of data ports of a communication system is disclosed. One method includes a first data port detecting a lack of data for transmission to a second data port. At least one of the first data port and a second data port deactivate electronic circuitry of at least one of the first and second data ports upon detection of the lack of data. The first and second data ports maintain synchronization with each other while the electronic circuitry is deactivated by periodically exchanging synchronization test patterns. At least one of the first data port and the second data port transmit an alert to the other of the first and second data port when data for communication is detected. The other of the first data port and the second data port activate electronic circuitry upon receiving the alert. At least one of the first data port and the second data port transmit data.
    Type: Application
    Filed: October 28, 2008
    Publication date: April 29, 2010
    Inventors: Dimitry Taich, Jose Tellado
  • Patent number: 7649868
    Abstract: A wireless link between a first transmitter and a first receiver in a multiple access communications system is evaluated by receiving, at the first transmitter, information that is intended for a second receiver and that is transmitted in a second transmission mode that is different from the current transmission mode and obtaining an error measure for the information that is received at the first receiver and intended for the second receiver. The obtained error measure is then used to determine if the second transmission mode is an acceptable transmission mode. In an embodiment, if the second transmission mode is determined to be acceptable, then the current transmission mode of the first receiver can be replaced by the second transmission mode. In an embodiment, the current transmission mode is replaced by the second transmission mode only if the second transmission mode is a “higher” transmission mode than the current transmission.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: January 19, 2010
    Assignee: Intel Corporation
    Inventors: Robert W. Heath, Jose Tellado
  • Patent number: 7646699
    Abstract: A device and method of setting transmit power backoff of a transceiver within a network is disclosed. The method includes estimating a channel loss of a channel of the transceiver, obtaining channel loss information, the channel loss information including estimates of channel loss of other channels of the network, obtaining crosstalk information, the crosstalk information including estimates of crosstalk between the channel and other channels of the network, and setting the power backoff based on the channel loss of the channel, the channel information, and the crosstalk information.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: January 12, 2010
    Assignee: Teranetics, Inc.
    Inventors: Jose Tellado, Sanjay Kasturia
  • Publication number: 20080233903
    Abstract: Embodiments of a method and apparatus for selecting coefficients of a non-linear filter are disclosed. The non-linear filter receives a transmit signal and generates a non-linear replica signal of a transmit DAC of a transceiver. The method include applying a plurality of periodic test pattern signals to inputs of the transmit DAC, wherein the periodic test pattern signals include a stream of symbols. Receive symbols are collected at an output of a receiver ADC of the transceiver resulting from the plurality of periodic test pattern signals. A non-linear map is generated that provides a value for each of n consecutive symbols input to the transmit DAC. Coefficients of the non-linear filter are selected based on the non-linear map.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 25, 2008
    Inventors: Dariush Dabiri, Jose Tellado
  • Publication number: 20080151792
    Abstract: An apparatus and method of aiding synchronization between a master transceiver and a slave transceiver is disclosed. The method includes the master transceiver transmitting data signals that are received by the slave transceiver. The slave transceiver locks a slave clock to the data signals with a slave phase-locked loop. The slave transceiver transmits slave clock information to the master transceiver.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Inventors: Dimitry Taich, Jose Tellado
  • Patent number: 7366231
    Abstract: Embodiments of an Ethernet transceiver are disclosed. The Ethernet transceiver includes a plurality of digital signal streams, at least one digital signal stream being coupled to another of the digital signal streams. A domain transformer transforms sub-blocks of each of the plurality of the digital signal streams from an original domain into a lower complexity domain. A processor joint processes the transformed sub-blocks of the digital signal streams, each joint processed digital signal stream sub-block is influenced by other digital signal streams sub-blocks. An inverse transformer inverse transforms the joint processed signal streams sub-blocks back to the original domain.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: April 29, 2008
    Assignee: Teranetics, Inc.
    Inventors: Jose Tellado, Sanjay Kasturia, Eran Cohan
  • Patent number: 7362791
    Abstract: A method and apparatus of joint processing a plurality of digital signal streams is disclosed. The method includes transforming a plurality of the digital signal streams from an original domain to a lower complexity processing domain. The transformed plurality of digital signal streams are joint processed, wherein the joint processing includes multiplying samples of the plurality of transformed digital signal streams by a processing matrix. The joint processed signal streams are inverse transformed back to the original domain. Diagonal elements of the processing matrix are adaptively selected to cancel transmission echo signals of the plurality digital signal streams introduced during transmission of the plurality digital signal streams depending upon signal coupling of the plurality of digital signal streams.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: April 22, 2008
    Assignee: Teranetics, Inc.
    Inventors: Jose Tellado, Sanjay Kasturia, Eran Cohan
  • Publication number: 20080049818
    Abstract: A method and apparatus for receiving one of a plurality of Ethernet transmission protocol signals is disclosed. Each transmission protocol signal includes a plurality of transmission signal streams. The method includes determining which of the transmission protocol signals is being received. An analog front-end processor is connected to one of a plurality of protocol digital processors based on the transmission protocol signal being received. A setting of at least one functional parameter of the analog front-end processor and/or the protocol digital processors is selected based on the transmission protocol signal being received. A sampling rate of the analog front-end processor and/or a processing rate of the protocol digital processors are selected based on the transmission protocol signal being received. The plurality of transmission signal streams of the transmission protocol signal being received by the analog front-end processor are ADC sampled based on a shared clock source.
    Type: Application
    Filed: August 28, 2006
    Publication date: February 28, 2008
    Inventors: Dimitry Taich, Jose Tellado
  • Patent number: 7333448
    Abstract: The invention includes a full duplex transceiver for transmitting and receiving communication signals. The transceiver includes 1 to N sample and hold circuits. Each sample and hold circuit receives a first signal that includes a far-end signal, and in some cases an echo signal, and in some cases alternatively or additionally cross-talk signals. The transceiver additionally includes a plurality of subtraction circuits. Each subtraction circuit receives an output of at least one of the sample and hold circuits. Each subtraction circuit subtracts at least a fraction of a replica signal from at least a fraction of the output of the at least one of the sample and hold circuits. The subtraction circuits generate an output that represent the far-end signal with substantially reduced echo and/or cross-talk interference, and is available for additional receiver processing.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: February 19, 2008
    Assignee: Teranetics, Inc.
    Inventors: Sandeep Kumar Gupta, Sanjay Kasturia, Jose Tellado
  • Publication number: 20070269022
    Abstract: An apparatus and method of setting power back-off of a master transceiver and a slave transceiver is disclosed. The method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.
    Type: Application
    Filed: May 22, 2006
    Publication date: November 22, 2007
    Inventors: Dimitry Taich, Jose Tellado
  • Publication number: 20070211794
    Abstract: Embodiments of a method and apparatus for reducing non-linear transmit signal components of a receive signal of a transceiver signal are disclosed. The method includes the transceiver simultaneously transmitting a transmit signal, and receiving the receive signal. A non-linear replica signal of non-linear transmission signal components that are created in the transceiver by a transmit signal DAC, and imposed onto the receive signal, is generated. The non-linear replica signal is subtracted from the received signal reducing the non-linear transmission signal components imposed onto the receive signal.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 13, 2007
    Inventors: Dariush Dabiri, Jose Tellado, Sandeep Gupta
  • Publication number: 20070165734
    Abstract: A method and apparatus of joint processing a plurality of digital signal streams is disclosed. The method includes transforming a plurality of the digital signal streams from an original domain to a lower complexity processing domain. The transformed plurality of digital signal streams are joint processed, wherein the joint processing includes multiplying samples of the plurality of transformed digital signal streams by a processing matrix. The joint processed signal streams are inverse transformed back to the original domain. Diagonal elements of the processing matrix are adaptively selected to cancel transmission echo signals of the plurality digital signal streams introduced during transmission of the plurality digital signal streams depending upon signal coupling of the plurality of digital signal streams.
    Type: Application
    Filed: February 5, 2007
    Publication date: July 19, 2007
    Inventors: Jose Tellado, Sanjay Kasturia, Eran Cohen
  • Publication number: 20070140289
    Abstract: A device and method of setting transmit power backoff of a transceiver within a network is disclosed. The method includes estimating a channel loss of a channel of the transceiver, obtaining channel loss information, the channel loss information including estimates of channel loss of other channels of the network, obtaining crosstalk information, the crosstalk information including estimates of crosstalk between the channel and other channels of the network, and setting the power backoff based on the channel loss of the channel, the channel information, and the crosstalk information.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 21, 2007
    Inventors: Jose Tellado, Sanjay Kasturia
  • Patent number: 7227883
    Abstract: A transceiver is disclosed. The transceiver includes a plurality of digital signal streams, wherein at least one digital signal stream is coupled to another of the digital signal streams. A transform block transforms a plurality of the digital signal streams from an original domain into a lower complexity processing domain. A processor joint processes the transformed digital signal streams, each joint processed digital signal stream being influenced by other digital signal streams. An inverse transform block inverse transforms the joint processed signal streams back to the original domain. A method of joint processing a plurality of digital signal streams is also disclosed. A first act of the method includes transforming a plurality of the digital signal streams from an original domain into a lower complexity processing domain.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: June 5, 2007
    Assignee: Teranetics, Inc.
    Inventors: Jose Tellado, Sanjay Kasturia, Eran Cohan
  • Publication number: 20070042721
    Abstract: A device and method for a full-duplex transceiver is disclosed. The transceiver includes a transmitter DAC coupled to a transmission channel. The transmit DAC converting a digital transmission signal into an analog transmission signal. The transceiver further includes a receiver connected to the transmission channel. The receiver receives a desired signal and an echo signal, in which the echo signal includes at least a portion of the analog transmission signal. The receiver includes a receiver ADC, a programmable delay line for adjustably delaying a clock signal of the ADC, and a receiver processing circuit for adjusting the delay of the clock signal based at least in part upon the echo signal.
    Type: Application
    Filed: August 17, 2005
    Publication date: February 22, 2007
    Inventors: Sandeep Gupta, Jose Tellado
  • Patent number: 7058146
    Abstract: A method for interference mitigation in a wireless communication system having multiple transmitters and receivers by introducing transmission time delays between the transmission of signals from the individual transmitters to ensure coherent reception of the signals at a specific point in the coverage area, such as at a center of distribution of the receivers. To further aid in interference mitigation the signals are assigned training patterns chosen to be distinguishable by the receiver and to optimize interference mitigation. The training patterns can be selected based on a feedback parameter, e.g., a measure of the quality of interference mitigation obtained from the receiver. The present method can be used in wireless communication systems which re-use frequencies including TDMA, CDMA, FDMA, OFDMA or other multiplex communication systems using a multiple access method or a combination of such methods.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Arogyaswami J. Paulraj, Peroor K. Sebastian, Jose Tellado, Robert W. Heath, Jr.
  • Publication number: 20060047857
    Abstract: Embodiments of a method and apparatus for decoding an Ethernet signal are disclosed. The method includes receiving an Ethernet bit stream. The bit stream is at least one of low-complexity decoded or high-complexity decoded. If the bit stream fails a low-complexity decoding test, then the bit stream is high-complexity decoded. The low-complexity decoding and high complexity decoding are iteratively repeated until the bit stream passes the low-complexity decoding test.
    Type: Application
    Filed: August 26, 2004
    Publication date: March 2, 2006
    Inventors: Dariush Dabiri, Jose Tellado
  • Publication number: 20050289204
    Abstract: Embodiments of a parallel feedback processor are disclosed. The parallel feedback processor includes a plurality of parallel coupled feedback filters. Each feedback filter includes a non-linear operator. At least one of feedback filter includes a plurality of sub-filters. Each sub-filter computes a one of possible non-linear operator filter outputs of the at least one feedback filter. One sub-filter output is selected as an output of the at least one feedback filter.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 29, 2005
    Inventors: Jose Tellado, Glenn Golden, Sanjay Kasturia, Jeffrey Hill, John Dring
  • Publication number: 20050135503
    Abstract: The invention includes an apparatus and a method for adjusting a power level of a transmission signal for minimal distortion. The method includes modulating the transmission signal. The modulated transmission signal is processed to reduce a peak to average ratio of the modulated transmission signal based upon modulation parameters of the modulated transmission signal. The power level of the modulated transmission signal is adjusted according to the peak to average ratio of the modulated transmission signal. The transmission signal is amplified and transmitted.
    Type: Application
    Filed: December 6, 2004
    Publication date: June 23, 2005
    Inventors: Shilpa Talwar, Jose Tellado