Patents by Inventor Jose YALLOUZ
Jose YALLOUZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240078283Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described.Type: ApplicationFiled: July 27, 2023Publication date: March 7, 2024Inventors: Amit GRADSTEIN, Simon RUBANOVICH, Sagi MELLER, Saeed KHAROUF, Gavri BERGER, Zeev SPERBER, Jose YALLOUZ, Ron SCHNEIDER
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Publication number: 20240036865Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: ApplicationFiled: June 17, 2023Publication date: February 1, 2024Inventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Patent number: 11765103Abstract: A data communication system includes a plurality of mutually-disjoint sets of switches, each set including multiple mutually-disjoint subsets of the switches in the set. Local links interconnect the switches within each of the subsets in a fully-connected topology, while none of the switches in any given subset are connected in a single hop to any of the switches in any other subset within the same set. Global links interconnect the sets of the switches, each global link connecting one switch in one of the sets to another switch in another one of the sets, such that each of the subsets in any given set of the switches is connected in a single hop by at least one global link to at least one of the subsets of every other set of the switches.Type: GrantFiled: December 1, 2021Date of Patent: September 19, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Michael Gandelman, Jose Yallouz
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Patent number: 11714875Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described.Type: GrantFiled: December 28, 2019Date of Patent: August 1, 2023Assignee: Intel CorporationInventors: Amit Gradstein, Simon Rubanovich, Sagi Meller, Saeed Kharouf, Gavri Berger, Zeev Sperber, Jose Yallouz, Ron Schneider
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Patent number: 11711318Abstract: Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.Type: GrantFiled: January 18, 2022Date of Patent: July 25, 2023Assignee: Mellanox Technologies Ltd.Inventors: Ioannis (Giannis) Patronas, Michael Gandelman, Liron Mula, Aviad Levy, Lion Levi, Jose Yallouz, Paraskevas Bakopoulos, Elad Mentovich
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Publication number: 20230224262Abstract: Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.Type: ApplicationFiled: January 18, 2022Publication date: July 13, 2023Inventors: Ioannis (Giannis) Patronas, Michael Gandelman, Liron Mula, Aviad Levy, Lion Levi, Jose Yallouz, Paraskevas Bakopoulos, Elad Mentovich
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Patent number: 11681530Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: GrantFiled: March 7, 2022Date of Patent: June 20, 2023Assignee: Intel CorporationInventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Publication number: 20230171206Abstract: A data communication system includes a plurality of mutually-disjoint sets of switches, each set including multiple mutually-disjoint subsets of the switches in the set. Local links interconnect the switches within each of the subsets in a fully-connected topology, while none of the switches in any given subset are connected in a single hop to any of the switches in any other subset within the same set. Global links interconnect the sets of the switches, each global link connecting one switch in one of the sets to another switch in another one of the sets, such that each of the subsets in any given set of the switches is connected in a single hop by at least one global link to at least one of the subsets of every other set of the switches.Type: ApplicationFiled: December 1, 2021Publication date: June 1, 2023Inventors: Michael Gandelman, Jose Yallouz
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Patent number: 11575594Abstract: A computing system including network elements arranged in at least one group. A plurality of the network elements are designated as spines and another plurality are designated as leaves, the spines and leaves are interconnected in a bipartite topology, and at least some of the spines and leaves are configured to: receive in a first leaf, from a source node, packets destined to a destination node via a second leaf, forward the packets via a first link to a first spine and to the second leaf via a second link, in response to detecting that the second link has failed, apply a detour path from the first leaf to the second leaf, including a detour link in a spine-to-leaf direction and another detour link a leaf-to-spine direction, and forward subsequent packets, which are received in the first leaf and are destined to the second leaf, via the detour path.Type: GrantFiled: September 10, 2020Date of Patent: February 7, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Jose Yallouz, Lion Levi, Tamir Ronen, Vladimir Koushnir, Neria Uzan
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Patent number: 11567772Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: GrantFiled: November 29, 2021Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Patent number: 11552882Abstract: A network element includes processing circuitry and multiple ports. The ports connect using links to a communication network. The processing circuitry is configured to receive packets via the ports and forward the received packets to respective destination addresses via the ports. The destination addresses are organized in address groups, each address group including multiple destination addresses of nodes connected to a common network element in the communication network. The processing circuitry is further configured to, in response to identifying that a given port connects to a faulty link, determine one or more address groups that became unreachable via the given port due to the faulty link, generate a notification reporting one or more of the determined address groups that are unreachable via any port other than the given port, and transmit the notification to one or more other network elements, via one or more ports other than the given port.Type: GrantFiled: March 25, 2021Date of Patent: January 10, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Jose Yallouz, Lion Levi, Gil Mey-Tal, Daniel Klein
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Publication number: 20220311702Abstract: A network element includes processing circuitry and multiple ports. The ports connect using links to a communication network. The processing circuitry is configured to receive packets via the ports and forward the received packets to respective destination addresses via the ports. The destination addresses are organized in address groups, each address group including multiple destination addresses of nodes connected to a common network element in the communication network. The processing circuitry is further configured to, in response to identifying that a given port connects to a faulty link, determine one or more address groups that became unreachable via the given port due to the faulty link, generate a notification reporting one or more of the determined address groups that are unreachable via any port other than the given port, and transmit the notification to one or more other network elements, via one or more ports other than the given port.Type: ApplicationFiled: March 25, 2021Publication date: September 29, 2022Inventors: Jose Yallouz, Lion Levi, Gil Mey-Tal, Daniel Klein
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Patent number: 11425027Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.Type: GrantFiled: November 1, 2020Date of Patent: August 23, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Michael Gandelman, Jose Yallouz, Lion Levi, Tamir Ronen, Aviad Levy, Vladimir Koushnir
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Publication number: 20220188114Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: ApplicationFiled: March 7, 2022Publication date: June 16, 2022Inventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Publication number: 20220174000Abstract: A switch, communication system, and method are provided. In one example, a communication system is described that includes a plurality of communication nodes and a switch that interconnects and facilitates a transmission of packets between the plurality of communication nodes. The communication system may be configured such that the packets are transmitted between the plurality of communication nodes by draining a demand matrix.Type: ApplicationFiled: December 1, 2020Publication date: June 2, 2022Inventors: Gal Mendelson, Jose Yallouz
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Publication number: 20220147356Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: ApplicationFiled: November 29, 2021Publication date: May 12, 2022Inventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Publication number: 20220141125Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.Type: ApplicationFiled: November 1, 2020Publication date: May 5, 2022Inventors: Michael Gandelman, Jose Yallouz, Lion Levi, Tamir Ronen, Aviad Levy, Vladimir Koushnir
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Publication number: 20220078104Abstract: A computing system including network elements arranged in at least one group. A plurality of the network elements are designated as spines and another plurality are designated as leaves, the spines and leaves are interconnected in a bipartite topology, and at least some of the spines and leaves are configured to: receive in a first leaf, from a source node, packets destined to a destination node via a second leaf, forward the packets via a first link to a first spine and to the second leaf via a second link, in response to detecting that the second link has failed, apply a detour path from the first leaf to the second leaf, including a detour link in a spine-to-leaf direction and another detour link a leaf-to-spine direction, and forward subsequent packets, which are received in the first leaf and are destined to the second leaf, via the detour path.Type: ApplicationFiled: September 10, 2020Publication date: March 10, 2022Inventors: Jose Yallouz, Lion Levi, Tamir Ronen, Vladimir Koushnir, Neria Uzan
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Patent number: 11188335Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: GrantFiled: November 2, 2020Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Patent number: 11176278Abstract: Integrated circuits to compute a result of summing m values, rotating the sum by k bits, and adding a summation of n values Bi to Bn to the rotated sum. An embodiment includes: a first carry save adder to add up the m values to generate a first carry and a first sum; rotator circuitry to rotate both the first carry and the first sum by k bits to generate a second carry and a second sum; a second carry save adder to add up the second carry, the second sum, and the summation of values Bi to Bn to generate a third carry and a third sum; two parallel adders to generate a first intermediate result and a second intermediary result based on the third carry and the third sum; and a multiplexer to generate the result utilizing various portions of the first and second intermediate results.Type: GrantFiled: December 29, 2018Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Amit Gradstein, Simon Rubanovich, Regev Shemy, Onkar P Desai, Jose Yallouz