Abstract: A supply power can be fed in at a circuit arrangement for supplying power to, and clocking, clocked loads. The circuit arrangement provides a clock signal at a frequency and a supply voltage, the frequency and/or the supply voltage being able to be controlled by the circuit arrangement in such a manner that a power tapped off at the output and the supply power fed in are in a predefined relationship.

Abstract: A method for changing a succession of instruction words including providing a set of machine words, each machine word being associated with an address from a set of addresses, providing a succession of instruction words having address information, the succession of instruction words prescribing a sequence of machine words which are intended to be processed by an arithmetic and logic unit which is coupled to a buffer store, altering the association between at least a portion of the set of machine words and at least a portion of the set of addresses, changing the address information in the succession of instruction words based on the alteration of the association, storing the changed succession of instruction words in a memory, and storing the set of machine words in the memory, so that it is possible to access the machine words using the associated addresses.

Abstract: A frequency regulator for varying a clock frequency of a power-supplied consumer operated in a clocked manner, wherein the frequency regulator is implemented to perform an overall variation of the clock frequency from an actual frequency to a set frequency, such that the overall variation is obtained by a plurality of clock changes, each with a different amount of change, wherein each of the respective amounts of change depends on a power change caused by the associated clock frequency change.

Abstract: Master-slave flip flop including a master latch having a data input for receiving a data input signal, an inverting clock input for receiving a first clock signal, and a data output, a slave latch having a data input which is connected to the data output of the master latch, a clock input for receiving a second clock signal, and a data output for outputting an output signal, and a time delay element connects the clock input of the slave latch to the clock input of the master latch.