Abstract: A signal processing circuit for a signal varying in its properties, e.g., in its degress of distortion, in which the input signal is fed in parallel to two similar processing circuits e.g., equalizers, the characteristic of which can be varied by a control signal, wherein the control signal from the one processing circuit is periodically varied and the output signal is fed to a detector circuit which in optimum signal processing emits a trigger pulse to a holding circuit 52 which stores the corresponding control signal level, which is fed to the second processing circuit.A variable delay unit for the data is controlled by a continuously varying up-down counter, the contents of which continuously vary at the rate of a high frequency clock pulse. The direction of count and the time of the count is controlled by comparing the relative time-positions or phases of a timing pulse received with the data and a timing pulse generated at the receiver.

Abstract: A signal processing circuit for a signal varying in its properties, e.g., in its degree of distortion, in which the input signal is fed in parallel to two similar processing circuits e.g., equalizers, the characteristic of which can be varied by a control signal, wherein the control signal from the one processing circuit is periodically varied and the output signal is fed to a detector circuit which in optimum signal processing emits a trigger pulse to a holding circuit 52 which stores the corresponding control signal level, which is fed to the second processing circuit.The detector circuit provided for an optimum equalization is a timing-pulse-controlled integrating circuit with a minimum detector connected at the output side. An application of the circuit for digital data transmission with the related synchronizing timing demodulator and phase control circuits is represented.

Abstract: A device for the automatic equalization, on the receiving side, of digital data signals, in which, after amplitude stabilization, the input signal is fed to a synchronizing unit and a clock signal generating unit, a distortion measuring unit and a controllable equalizer unit in which the distortion measuring signal is fed to the equalizer as a control signal. The output signal of the equalizer is then normalized in amplitude. The equalization measuring unit consists of a squaring or rectifier unit, a clock filter for the zero transition region and an integrator. Equalizers with different characteristics and their circuits are represented. The amplitude stabilization on the input side may be supplemented by an amplitude-controlled pre-equalization (FIG. 1).