Patents by Inventor Josef Maynollo
Josef Maynollo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8729659Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner.Type: GrantFiled: March 18, 2013Date of Patent: May 20, 2014Assignee: Infineon Technologies AGInventor: Josef Maynollo
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Patent number: 8603912Abstract: A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, while avoiding electrically insulating additional protection and sealing layers that are usually to be provided.Type: GrantFiled: September 6, 2011Date of Patent: December 10, 2013Assignee: Infineon Technologies AGInventors: Josef Maynollo, Thomas Detzel
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Patent number: 8399956Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner.Type: GrantFiled: February 20, 2009Date of Patent: March 19, 2013Assignee: Infineon Technologies AGInventor: Josef Maynollo
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Publication number: 20110318883Abstract: A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided.Type: ApplicationFiled: September 6, 2011Publication date: December 29, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Josef Maynollo, Thomas Detzel
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Patent number: 8039931Abstract: A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided.Type: GrantFiled: November 28, 2005Date of Patent: October 18, 2011Assignee: Infineon Technologies AGInventors: Josef Maynollo, Thomas Detzel
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Patent number: 7947431Abstract: Lithography masks and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of manufacturing a lithography mask. The method includes providing a substrate, forming a first pattern in a first region of the substrate, and forming a second pattern in a second region of the substrate, the second pattern comprising patterns for features oriented differently than patterns for features of the first pattern. The method includes affecting a polarization rotation of light differently in the first region than in the second region of the substrate.Type: GrantFiled: July 30, 2010Date of Patent: May 24, 2011Assignee: Infineon Technologies AGInventors: Chandrasekhar Sarma, Alois Gutmann, Henning Haffner, Sajan Marokkey, Josef Maynollo
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Publication number: 20100297398Abstract: Lithography masks and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of manufacturing a lithography mask. The method includes providing a substrate, forming a first pattern in a first region of the substrate, and forming a second pattern in a second region of the substrate, the second pattern comprising patterns for features oriented differently than patterns for features of the first pattern. The method includes affecting a polarization rotation of light differently in the first region than in the second region of the substrate.Type: ApplicationFiled: July 30, 2010Publication date: November 25, 2010Inventors: Chandrasekhar Sarma, Alois Gutmann, Henning Haffner, Sajan Marokkey, Josef Maynollo
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Patent number: 7799486Abstract: Lithography masks and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of manufacturing a lithography mask. The method includes providing a substrate, forming a first pattern in a first region of the substrate, and forming a second pattern in a second region of the substrate, the second pattern comprising patterns for features oriented differently than patterns for features of the first pattern. The method includes affecting a polarization rotation of light differently in the first region than in the second region of the substrate.Type: GrantFiled: November 21, 2006Date of Patent: September 21, 2010Assignee: Infineon Technologies AGInventors: Chandrasekhar Sarma, Alois Gutmann, Henning Haffner, Sajan Marokkey, Josef Maynollo
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Patent number: 7713824Abstract: A method for controlling etching during photolithography in the fabrication of an integrated circuit in connection with first and second features that are formed on the integrated circuit having a gap there between comprising depositing a layer of photoresist on the integrated circuit, selectively exposing portions of the photoresist through at least one photolithography mask having a pattern including means for alleviating line end shortening of the first and second lines adjacent the gap, and developing the photoresist after the selective exposing step.Type: GrantFiled: February 21, 2007Date of Patent: May 11, 2010Assignee: Infineon Technologies North America Corp.Inventors: Chandrasekhar Sarma, Alois Gutmann, Sajan Marokkey, Josef Maynollo
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Publication number: 20090152672Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner.Type: ApplicationFiled: February 20, 2009Publication date: June 18, 2009Inventor: Josef Maynollo
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Patent number: 7498232Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner.Type: GrantFiled: July 24, 2006Date of Patent: March 3, 2009Assignee: Infineon Technologies AGInventor: Josef Maynollo
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Publication number: 20080199784Abstract: A method for controlling etching during photolithography in the fabrication of an integrated circuit in connection with first and second features that are formed on the integrated circuit having a gap there between comprising depositing a layer of photoresist on the integrated circuit, selectively exposing portions of the photoresist through at least one photolithography mask having a pattern including means for alleviating line end shortening of the first and second lines adjacent the gap, and developing the photoresist after the selective exposing step.Type: ApplicationFiled: February 21, 2007Publication date: August 21, 2008Applicant: Infineon Technologies North America Corp.Inventors: Chandrasekhar Sarma, Alois Gutmann, Sajan Raphael Marokkey, Josef Maynollo
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Publication number: 20080119048Abstract: Lithography masks and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of manufacturing a lithography mask. The method includes providing a substrate, forming a first pattern in a first region of the substrate, and forming a second pattern in a second region of the substrate, the second pattern comprising patterns for features oriented differently than patterns for features of the first pattern. The method includes affecting a polarization rotation of light differently in the first region than in the second region of the substrate.Type: ApplicationFiled: November 21, 2006Publication date: May 22, 2008Inventors: Chandrasekhar Sarma, Alois Gutmann, Henning Haffner, Sajan Marokkey, Josef Maynollo
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Patent number: 7364975Abstract: Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece including a plurality of active area regions defined therein, and forming at least one trench in the workpiece between at least two of the plurality of active area regions. A first insulating material is deposited over the plurality of active area regions and the at least one trench, partially filling the at least one trench with the first insulating material and forming peaks of the first insulating material over the plurality of active area regions. A masking material is formed over the first insulating material in the at least one trench, leaving the peaks of the first insulating material over the plurality of active area regions completely exposed. At least the peaks of the first insulating material are removed from over the plurality of active area regions.Type: GrantFiled: July 20, 2006Date of Patent: April 29, 2008Assignee: Infineon Technologies AGInventors: Marcus Culmsee, Frank Weber, Josef Maynollo
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Publication number: 20080020542Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner.Type: ApplicationFiled: July 24, 2006Publication date: January 24, 2008Inventor: Josef Maynollo
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Publication number: 20080020534Abstract: Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece including a plurality of active area regions defined therein, and forming at least one trench in the workpiece between at least two of the plurality of active area regions. A first insulating material is deposited over the plurality of active area regions and the at least one trench, partially filling the at least one trench with the first insulating material and forming peaks of the first insulating material over the plurality of active area regions. A masking material is formed over the first insulating material in the at least one trench, leaving the peaks of the first insulating material over the plurality of active area regions completely exposed. At least the peaks of the first insulating material are removed from over the plurality of active area regions.Type: ApplicationFiled: July 20, 2006Publication date: January 24, 2008Inventors: Marcus Culmsee, Frank Weber, Josef Maynollo
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Publication number: 20060145342Abstract: A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided.Type: ApplicationFiled: November 28, 2005Publication date: July 6, 2006Inventors: Josef Maynollo, Thomas Detzel