Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; an upper conductor extending above, without contacting, the source/drain contact, wherein the upper conductor extends within the dielectric layer to contact the gate conductor within the gate stack.

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; an upper conductor extending above, without contacting, the source/drain contact, wherein the upper conductor extends within the dielectric layer to contact the gate conductor within the gate stack.

Abstract: A method of forming an integrated circuit includes forming a FinFET by: forming a semiconductor fin on a semiconductor substrate; forming a first source/drain region in the semiconductor substrate under a first end of the semiconductor fin and a second source/drain region in the semiconductor substrate under a second, opposing end of the semiconductor fin, the second source/drain region separated from the first source/drain region by a portion of the semiconductor substrate having an opposite doping from that of the first and second source/drain region; and forming a surrounding gate extending about the semiconductor fin above the semiconductor substrate. A second vertical FinFET may be formed simultaneously. The method allows the FinFET to have a long channel extending laterally through its fin compared to the short channel of the vertical FinFET, thus creating short channel and long channel devices together without impacting vertical FinFET height.

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; a conductor extending above, without contacting, the source/drain contact and extending within the dielectric layer to contact the gate conductor within the gate stack.

Abstract: Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (fT) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (Vd1); extracting a transconductance (Gm) from the first set of in-line DC parameters as a function of a gate-voltage (Vg) and the first drain-voltage (Vd1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (Vd2); extracting a total gate capacitance (Cgg) from the second set of in-line DC parameters as a function of the gate-voltage (Vg); and predicting the unity gain frequency (fT) of the MOSFET based upon the extracted transconductance (Gm) and the extracted total gate capacitance (Cgg).

Abstract: The disclosure provides a vertical FinFET structure, including: a substrate including a first source/drain region; a looped channel region positioned on the first source/drain region of the substrate, the looped channel region having an inner perimeter which surrounds a hollow interior of the looped channel region; a first gate positioned within the hollow interior of the looped channel region, wherein the first gate is formed onto the looped channel region along the inner perimeter of the looped channel region; and a second source/drain region positioned on and overlying an upper surface of the looped channel region.

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; a conductor extending above, without contacting, the source/drain contact and extending within the dielectric layer to contact the gate conductor within the gate stack.

Abstract: Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (fT) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (Vd1); extracting a transconductance (Gm) from the first set of in-line DC parameters as a function of a gate-voltage (Vg) and the first drain-voltage (Vd1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (Vd2); extracting a total gate capacitance (Cgg) from the second set of in-line DC parameters as a function of the gate-voltage (Vg); and predicting the unity gain frequency (fT) of the MOSFET based upon the extracted transconductance (Gm) and the extracted total gate capacitance (Cgg).

Abstract: Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (fT) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (Vd1); extracting a transconductance (Gm) from the first set of in-line DC parameters as a function of a gate-voltage (Vg) and the first drain-voltage (Vd1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (Vd2); extracting a total gate capacitance (Cgg) from the second set of in-line DC parameters as a function of the gate-voltage (Vg); and predicting the unity gain frequency (fT) of the MOSFET based upon the extracted transconductance (Gm) and the extracted total gate capacitance (Cgg).

Abstract: Various embodiments provide computer program products and computer implemented methods. In some embodiments, aspects provide for a method of manufacturing a polysilicon resistor with a selected temperature coefficient of resistance (TCR), the method including selecting a sheet resistance for the polysilicon resistor, the selected sheet resistance being related to a selected film thickness of the polysilicon resistor, selecting a dose level for a grain size modulating species (GSMS) for modulating an average grain size of grains of the polysilicon resistor, selecting a thermal coefficient of resistance (TCR) for the polysilicon resistor, the TCR being related to a selected average grain size of the polysilicon and forming the polysilicon resistor on a substrate, the polysilicon resistor having the selected sheet resistance, the selected GSMS dose level and the selected TCR.

Abstract: Various embodiments provide computer program products and computer implemented methods. In some embodiments, aspects provide for a method of manufacturing a polysilicon resistor with a selected temperature coefficient of resistance (TCR), the method including selecting a sheet resistance for the polysilicon resistor, the selected sheet resistance being related to a selected film thickness of the polysilicon resistor, selecting a dose level for a grain size modulating species (GSMS) for modulating an average grain size of grains of the polysilicon resistor, selecting a thermal coefficient of resistance (TCR) for the polysilicon resistor, the TCR being related to a selected average grain size of the polysilicon and forming the polysilicon resistor on a substrate, the polysilicon resistor having the selected sheet resistance, the selected GSMS dose level and the selected TCR.

Abstract: Methods, program products, and systems for improving optical proximity correction (OPC) calibration, and automatically determining a minimal number of clips, are disclosed. The method can include using a computing device to perform actions including: calculating a total relevancy score for a projected sample plan including a candidate clip, and wherein the relevancy score is derived from at least one relevancy criterion and a relevancy weight; calculating a relevancy score for the candidate clip, the relevancy score for the candidate clip being a contribution from the candidate clip to the total relevancy score; and adding the candidate clip to a sample plan for the IC layout and removing the candidate clip from the plurality of clips in response a difference in relevancy score between the projected sample plan and one or more previous sample plans substantially fitting a non-linear relevancy score function.

Abstract: Methods, program products, and systems for improving optical proximity correction (OPC) calibration, and automatically determining a minimal number of clips, are disclosed. The method can include using a computing device to perform actions including: calculating a total relevancy score for a projected sample plan including a candidate clip, and wherein the relevancy score is derived from at least one relevancy criterion and a relevancy weight; calculating a relevancy score for the candidate clip, the relevancy score for the candidate clip being a contribution from the candidate clip to the total relevancy score; and adding the candidate clip to a sample plan for the IC layout and removing the candidate clip from the plurality of clips in response a difference in relevancy score between the projected sample plan and one or more previous sample plans substantially fitting a non-linear relevancy score function.

Abstract: Various embodiments provide computer program products and computer implemented methods. In some embodiments, aspects provide for a method of manufacturing a polysilicon resistor with a selected temperature coefficient of resistance (TCR), the method including selecting a sheet resistance for the polysilicon resistor, the selected sheet resistance being related to a selected film thickness of the polysilicon resistor, selecting a dose level for a grain size modulating species (GSMS) for modulating an average grain size of grains of the polysilicon resistor, selecting a thermal coefficient of resistance (TCR) for the polysilicon resistor, the TCR being related to a selected average grain size of the polysilicon and forming the polysilicon resistor on a substrate, the polysilicon resistor having the selected sheet resistance, the selected GSMS dose level and the selected TCR.

Abstract: Various embodiments provide computer program products and computer implemented methods. In some embodiments, aspects provide for a method of manufacturing a polysilicon resistor with a selected temperature coefficient of resistance (TCR), the method including selecting a sheet resistance for the polysilicon resistor, the selected sheet resistance being related to a selected film thickness of the polysilicon resistor, selecting a dose level for a grain size modulating species (GSMS) for modulating an average grain size of grains of the polysilicon resistor, selecting a thermal coefficient of resistance (TCR) for the polysilicon resistor, the TCR being related to a selected average grain size of the polysilicon and forming the polysilicon resistor on a substrate, the polysilicon resistor having the selected sheet resistance, the selected GSMS dose level and the selected TCR.

Abstract: Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (fT) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (Vd1); extracting a transconductance (Gm) from the first set of in-line DC parameters as a function of a gate-voltage (Vg) and the first drain-voltage (Vd1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (Vd2); extracting a total gate capacitance (Cgg) from the second set of in-line DC parameters as a function of the gate-voltage (Vg); and predicting the unity gain frequency (fT) of the MOSFET based upon the extracted transconductance (Gm) and the extracted total gate capacitance (Cgg).