Abstract: A latch-up protection circuit for an integrated circuit using complementary MOS circuit technology has a substrate bias generator that applies a negative substrate bias to a semiconductor substrate having a p-conductive material into which a well-shaped semiconductor zone of n-conductive material is inserted. In order to avoid latch-up effects in the integrated circuit, an electronic protection circuit interrupts the capacitive charging currents of a capacitor in the substrate depending on the potential of the semiconductor substrate which is taken at a doped substrate bias terminal. The electronic protection circuit disconnects a capacitor bias generator from the capacitor when a voltage on the substrate bias terminal is greater than a difference between a reference potential and a threshold voltage of a first transistor in the electronic protection circuit.

Abstract: A latch-up protection circuit for an integrated circuit using complementary MOS circuit technology has a substrate bias generator that applies a negative substrate bias to a semiconductor substrate having a p-conductive material into which a well-shaped semiconductor zone of n-conductive material is inserted. In order to avoid latch-up effects in the integrated circuit, an electronic protection circuit interrupts the capacitive charging currents of a capacitor in the substrate depending on the potential of the semiconductor substrate which is taken at a doped substrate bias terminal. The electronic protection circuit connects a capacitor bias generator to the capacitor when a voltage on the substrate bias terminal is less than a sum of a reference potential and a threshold voltage of a first transistor in the electronic protection circuit. The electronic protection circuit disconnects the capacitive bias generator from the capacitor when a voltage on the substrate bias terminal is greater than the sum.

Abstract: A method for the manufacture of LSI complementary MOS field effect transistor circuits to increase the latch-up hardness of the n-channel and p-channel field effect transistors while retaining good transistor properties by incorporating a further epitaxial layer and highly doped implantation regions into a lower epitaxial layer from which the wells are generated by out-diffusion into the upper epitaxial layer. In addition to achieving optimum transistor properties, the reduced lateral diffusion provided enables a lower n.sup.+ /p.sup.+ spacing, and thus achieves a higher packing density with improved latch-up hardness.

Abstract: A method for the simultaneous manufacture of bipolar and complementary MOS transistors on a common silicon substrate, wherein n-doped wells are produced in a p-doped substrate for accepting p-channel transistors and npn bipolar transistors are formed into the n-doped wells, the n-well forming the collector of the transistor and the n-wells overlying buried n.sup.+ -doped zones which are connected in the bipolar transistor region by more deeply extending collector plugs. A buried part and plug region of the collector are produced before the production of the wells, and the collector region is formed in the substrate in common with the well so the high-temperature step after the conventional LOCOS process is eliminated. The well implantation is self-adjusting relative to the implantation of the deep collector plug which is annularly formed in the well. A reduction of the collector series resistance as well as an increased latch-up hardness is obtained. Further, the parasitic substrate-pnp is reduced.