Patents by Inventor Joseph A. Yedinak

Joseph A. Yedinak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Trench-based power semiconductor devices with increased breakdown voltage characteristics
    Patent number: 10868113
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 15, 2020
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Joseph A. Yedinak, Ashok Challa, Dean E. Probst, Daniel Kinzer
  • Methods and apparatus related to termination regions of a semiconductor device
    Patent number: 10749027
    Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 18, 2020
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Richard Stokes, Jason Higgs, Fred Session
  • Termination implant enrichment for shielded gate MOSFETS
    Patent number: 10446640
    Abstract: In a general aspect, a power semiconductor device can include a first trench shield electrode and a second trench shield electrode defined in a semiconductor region, the first and second trench shield electrodes each having a first portion disposed in an active region and a second portion disposed in a termination region. A trench of the first trench shield electrode and a trench of the second trench shield electrode can define a mesa of the semiconductor region therebetween. The device can further include an implant enrichment region disposed in the termination region, the implant enrichment region can have a plurality of segments, at least one of the segments being disposed in the mesa. The trench shield electrodes can be disposed between segments of the implant enrichment region.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: October 15, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Joseph Yedinak, Xiaoli Wu
  • METHODS AND APPARATUS RELATED TO TERMINATION REGIONS OF A SEMICONDUCTOR DEVICE
    Publication number: 20190245078
    Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.
    Type: Application
    Filed: December 28, 2018
    Publication date: August 8, 2019
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Joseph A. Yedinak, Richard Stokes, Jason Higgs, Fred Session
  • Shield indent trench termination for shielded gate MOSFETs
    Patent number: 10374076
    Abstract: In a general aspect, a power semiconductor device can include a semiconductor region having an active region and a termination region. The device can also include a plurality of trench shield electrodes each having a first portion disposed in the active region and a second portion disposed in the termination region. One or more of the trench shield electrodes can have a second portion that extends a first distance into the termination region, while one or more other trench shield electrodes can have a second portion that extends a second distance into the termination region, the second distance being less than the first distance. The trench shield electrode(s) having the second portion that extends the second distance into the termination region can be interleaved with the trench shield electrode(s) having the second portion that extends the first distance into the termination region.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Xiaoli Wu, Joseph Yedinak
  • TERMINATION IMPLANT ENRICHMENT FOR SHIELDED GATE MOSFETS
    Publication number: 20190157383
    Abstract: In a general aspect, a power semiconductor device can include a first trench shield electrode and a second trench shield electrode defined in a semiconductor region, the first and second trench shield electrodes each having a first portion disposed in an active region and a second portion disposed in a termination region. A trench of the first trench shield electrode and a trench of the second trench shield electrode can define a mesa of the semiconductor region therebetween. The device can further include an implant enrichment region disposed in the termination region, the implant enrichment region can have a plurality of segments, at least one of the segments being disposed in the mesa. The trench shield electrodes can be disposed between segments of the implant enrichment region.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Joseph YEDINAK, Xiaoli WU
  • Termination implant enrichment for shielded gate MOSFETs
    Patent number: 10236340
    Abstract: In a general aspect, a power semiconductor device can include a first trench shield electrode and a second trench shield electrode defined in a semiconductor region, the first and second trench shield electrodes each having a first portion disposed in an active region and a second portion disposed in a termination region. A trench of the first trench shield electrode and a trench of the second trench shield electrode can define a mesa of the semiconductor region therebetween. The device can further include an implant enrichment region disposed in the termination region, the implant enrichment region can be intersected by the first trench shield electrode and the second trench shield electrode, and can have a portion disposed in the mesa of the semiconductor region, the portion extending from the trench of the first trench shield electrode to the trench of the second trench shield electrode.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Joseph Yedinak, Xiaoli Wu
  • SHIELD INDENT TRENCH TERMINATION FOR SHIELDED GATE MOSFETS
    Publication number: 20190006512
    Abstract: In a general aspect, a power semiconductor device can include a semiconductor region having an active region and a termination region. The device can also include a plurality of trench shield electrodes each having a first portion disposed in the active region and a second portion disposed in the termination region. One or more of the trench shield electrodes can have a second portion that extends a first distance into the termination region, while one or more other trench shield electrodes can have a second portion that extends a second distance into the termination region, the second distance being less than the first distance. The trench shield electrode(s) having the second portion that extends the second distance into the termination region can be interleaved with the trench shield electrode(s) having the second portion that extends the first distance into the termination region.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Xiaoli WU, Joseph Yedinak
  • TERMINATION IMPLANT ENRICHMENT FOR SHIELDED GATE MOSFETS
    Publication number: 20180315812
    Abstract: In a general aspect, a power semiconductor device can include a first trench shield electrode and a second trench shield electrode defined in a semiconductor region, the first and second trench shield electrodes each having a first portion disposed in an active region and a second portion disposed in a termination region. A trench of the first trench shield electrode and a trench of the second trench shield electrode can define a mesa of the semiconductor region therebetween. The device can further include an implant enrichment region disposed in the termination region, the implant enrichment region can be intersected by the first trench shield electrode and the second trench shield electrode, and can have a portion disposed in the mesa of the semiconductor region, the portion extending from the trench of the first trench shield electrode to the trench of the second trench shield electrode.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 1, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Joseph YEDINAK, Xiaoli WU
  • TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS
    Publication number: 20180012958
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Application
    Filed: August 28, 2017
    Publication date: January 11, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Joseph A. YEDINAK, Ashok CHALLA, Dean E. PROBST, Daniel KINZER
  • Trench-based power semiconductor devices with increased breakdown voltage characteristics
    Patent number: 9748329
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: August 29, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Ashok Challa
  • Superjunction structures for power devices
    Patent number: 9595596
    Abstract: In one general aspect, a power device can include an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type. The power device can include a termination region surrounding at least a portion of the active region and can have a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type. Each of the plurality of pillars of the first conductivity type in the active region and the termination region can be defined by a trench. The power device can include an enrichment region at a bottom portion of one of the plurality of pillars of the first conductivity type in the active region.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: March 14, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Jaegil Lee, Chongman Yun, Praveen Muraleedharan Shenoy, Christopher L. Rexer
  • Ignition control circuit with dual (two-stage) clamp
    Patent number: 9559498
    Abstract: In a general aspect, an apparatus can include an insulated gate bipolar transistor (IGBT) device configured to control charging and discharging of an ignition coil and a two-stage voltage clamp coupled with the IGBT device. The two-stage voltage clamp can include a high-voltage portion coupled with the IGBT device and a low-voltage portion coupled with high-voltage portion and the IGBT device. The apparatus can further include a sense device coupled with the two-stage voltage clamp and a timing circuit coupled with the sense device. The timing circuit can be configured to provide a control signal to cause the sense device to enable or disable the high-voltage portion of the two-stage voltage clamp.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: January 31, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Scott Pearson
  • METHODS AND APPARATUS RELATED TO TERMINATION REGIONS OF A SEMICONDUCTOR DEVICE
    Publication number: 20170012099
    Abstract: In one general aspect, an apparatus can include a semiconductor region having an active region, and an end trench defined within a termination region of the semiconductor region where the end trench has a curved shape.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Inventors: Joseph A. YEDINAK, Richard STOKES
  • MOSFET bridge circuit
    Patent number: 9509227
    Abstract: In a general aspect, a bridge circuit can include a first bridge including a first plurality of MOSFETs and including a first input terminal and a second input terminal, and a second bridge including a second plurality of MOSFETs and including a third input terminal and a fourth input terminal. The first bridge and the second bridge can be coupled in parallel and being coupled to a first load terminal and a second load terminal.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: November 29, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Scott Pearson, Mark L. Rinehimer, Sungjin Kuen
  • Termination region of a semiconductor device
    Patent number: 9496391
    Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: November 15, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Richard Stokes, Jason Higgs, Fred Session
  • Trench-based power semiconductor devices with increased breakdown voltage characteristics
    Patent number: 9391193
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: July 12, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Ashok Challa, Daniel M. Kinzer, Dean E. Probst, Daniel Calafut
  • Trench-based power semiconductor devices with increased breakdown voltage characteristics
    Patent number: 9293526
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: March 22, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Ashok Challa, Dean Probst
  • IGNITION CONTROL CIRCUIT WITH DUAL (TWO-STAGE) CLAMP
    Publication number: 20150288151
    Abstract: In a general aspect, an apparatus can include an insulated gate bipolar transistor (IGBT) device configured to control charging and discharging of an ignition coil and a two-stage voltage clamp coupled with the IGBT device. The two-stage voltage clamp can include a high-voltage portion coupled with the IGBT device and a low-voltage portion coupled with high-voltage portion and the IGBT device. The apparatus can further include a sense device coupled with the two-stage voltage clamp and a timing circuit coupled with the sense device. The timing circuit can be configured to provide a control signal to cause the sense device to enable or disable the high-voltage portion of the two-stage voltage clamp.
    Type: Application
    Filed: March 27, 2015
    Publication date: October 8, 2015
    Inventors: Joseph A. YEDINAK, Scott PEARSON
  • TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS
    Publication number: 20150206937
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Application
    Filed: March 26, 2015
    Publication date: July 23, 2015
    Inventors: Joseph A. Yedinak, Ashok Challa