Patents by Inventor Joseph B. Tompkins
Joseph B. Tompkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9680742Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: GrantFiled: February 28, 2014Date of Patent: June 13, 2017Assignee: Cavium, Inc.Inventors: Joseph B. Tompkins, Brian Robert Folsom, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins, Krupa Sagar O. S. Mylavarapu, Mahesh Dorai, Nagaraj G. Shirali, Ranjith Kumar V. Hallur
-
Patent number: 9559982Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: GrantFiled: February 28, 2014Date of Patent: January 31, 2017Assignee: Cavium, Inc.Inventors: Brian Robert Folsom, Joseph B. Tompkins, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins
-
Patent number: 9397938Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: GrantFiled: February 28, 2014Date of Patent: July 19, 2016Assignee: Cavium, Inc.Inventors: Brian Robert Folsom, Joseph B. Tompkins, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins
-
Publication number: 20150249604Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Applicant: CAVIUM, INC.Inventors: Brian Robert Folsom, Joseph B. Tompkins, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins
-
Publication number: 20150249603Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Applicant: Cavium, Inc.Inventors: Joseph B. Tompkins, Brian Robert Folsom, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins, Krupa Sagar O.S. Mylavarapu, Mahesh Dorai, Nagaraj G. Shirali, Ranjith Kumar V. Hallur
-
Publication number: 20150249620Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Applicant: Cavium, Inc.Inventors: Brian Robert Folsom, Joseph B. Tompkins, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins
-
Patent number: 7099328Abstract: An integrated circuit for processing communication packets having separate data buffers and separate state information buffers. Each data buffer and each state information buffer (hereinafter termed resources) has an associated in-use counter. Multiple events can share the same resource. The counter associated with a resource is incremented when a resource becomes associated with a particular event. The counter associated with a resource is decremented when an event completes the use of that particular resource. When the in-use counter for a resource becomes zero, the in-use counter indicates that the resource is unassigned and that the resource can be assigned to a new event.Type: GrantFiled: July 31, 2001Date of Patent: August 29, 2006Assignee: Mindspeed Technologies, Inc.Inventors: Duane E. Galbi, Joseph B. Tompkins, Bruce G. Burns, Daniel J. Lussier
-
Patent number: 7046686Abstract: An integrated circuit processes communication packets and comprises a pointer cache and control logic. The pointer cache store pointers that correspond to external buffers that are external to the integrated circuit and configured to store the communication packets. The control logic allocates the external buffers as the corresponding pointers are read from the pointer cache and de-allocates the external buffers as the corresponding pointers are written back to the pointer cache.Type: GrantFiled: August 16, 2000Date of Patent: May 16, 2006Assignee: Mindspeed Technologies, Inc.Inventors: Joseph B. Tompkins, Daniel J. Lussier, Wilson P. Snyder, II
-
Patent number: 6888830Abstract: An integrated circuit processes a communication packet and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packet. The scheduling circuitry retrieves first scheduling parameters cached in a context buffer for the packet and executes a first algorithm based on the first scheduling parameters to schedule subsequent transmission of the communication packet.Type: GrantFiled: August 16, 2000Date of Patent: May 3, 2005Assignee: Mindspeed Technologies, Inc.Inventors: Wilson P. Snyder II, Joseph B. Tompkins, Daniel J. Lussier
-
Publication number: 20040202192Abstract: An integrated circuit for processing communication packets having separate data buffers and separate state information buffers. Each data buffer and each state information buffer (hereinafter termed resources) has an associated in-use counter. Multiple events can share the same resource. The counter associated with a resource is incremented when a resource becomes associated with a particular event. The counter associated with a resource is decremented when an event completes the use of that particular resource. When the in-use counter for a resource becomes zero, the in-use counter indicates that the resource is unassigned and that the resource can be assigned to a new event.Type: ApplicationFiled: July 31, 2001Publication date: October 14, 2004Inventors: Duane E. Galbi, Joseph B. Tompkins, Bruce G. Burns, Daniel J. Lussier
-
Patent number: 6804239Abstract: An integrated circuit comprises co-processor circuitry and a core processor. The co-processor circuitry comprises context buffers and data buffers. The co-processor circuitry receives and stores one of the communication packets in one of the data buffers. The co-processor circuitry correlates the one communication packet with one of a plurality of channel descriptors. The co-processor circuitry associates the one data buffer with one of the context buffers holding the one channel descriptor to maintain the correlation between the one communication packet and the one channel descriptor. The co-processor circuitry prevents multiple valid copies of the one channel descriptor from existing in the context buffers. In some examples of the invention, this is accomplished by tracking a number of the data buffers associated with the one context buffer.Type: GrantFiled: August 16, 2000Date of Patent: October 12, 2004Assignee: Mindspeed Technologies, Inc.Inventors: Daniel J. Lussier, Joseph B. Tompkins, Wilson P. Snyder II
-
Patent number: 6760337Abstract: An integrated circuit processes communication packets and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packets. The scheduling circuitry comprises multiple scheduling boards where at least some of the scheduling boards have multiple priority levels. The scheduling circuitry processes the scheduling boards to schedule and subsequently initiate transmission of the communication packets.Type: GrantFiled: August 16, 2000Date of Patent: July 6, 2004Assignee: Conexant Systems, Inc.Inventors: Wilson P. Snyder, II, Joseph B. Tompkins, Daniel J. Lussier
-
Patent number: 6754223Abstract: An integrated circuit processes communication packets and comprises co-processor circuitry and a core processor. The co-processor circuitry is configured to operate in parallel with the core processor. The co-processor circuitry receives and stores the communication packets in data buffers. The co-processor circuitry also determines a prioritized processing order. The core processor executes a packet processing software application that directs the processor to process the communication packets in the data buffers based on the prioritized processing order.Type: GrantFiled: August 16, 2000Date of Patent: June 22, 2004Assignee: Conexant Systems, Inc.Inventors: Daniel J. Lussier, Joseph B. Tompkins, Wilson P. Snyder, II
-
Publication number: 20020051460Abstract: An integrated circuit for processing communication packets having separate data buffers and separate state information buffers. Each data buffer and each state information buffer (hereinafter termed resources) has an associated in-use counter. Multiple events can share the same resource. The counter associated with a resource is incremented when a resource becomes associated with a particular event. The counter associated with a resource is decremented when an event completes the use of that particular resource. When the in-use counter for a resource becomes zero, the in-use counter indicates that the resource is unassigned and that the resource can be assigned to a new event.Type: ApplicationFiled: July 31, 2001Publication date: May 2, 2002Inventors: Duane E. Galbi, Joseph B. Tompkins, Bruce G. Burns, Daniel J. Lussier
-
Patent number: RE42092Abstract: An integrated circuit processes communication packets and comprises a pointer cache and control logic. The pointer cache store pointers that correspond to external buffers that are external to the integrated circuit and configured to store the communication packets. The control logic allocates the external buffers as the corresponding pointers are read from the pointer cache and de-allocates the external buffers as the corresponding pointers are written back to the pointer cache.Type: GrantFiled: May 16, 2008Date of Patent: February 1, 2011Inventors: Joseph B. Tompkins, Daniel J. Lussier, Wilson P. Snyder, II