Abstract: A plated plastic castellated interconnect comprises a substrate made from a molded polymeric material and having top and bottom surfaces with a plurality of separate mutually spaced apart castellations integrally molded to the substrate and projecting from the bottom surface of the substrate. A plurality of separate spaced apart recessed regions may be molded in an edge of the substrate and aligned with the castellations. A plurality of metal conductors are plated to the substrate as separate conductive circuit traces, so that each circuit trace extends continuously from the top surface, along the surface of a corresponding recess and to a common plane on a respective castellation at the bottom of the substrate. The plated metal castellations are arranged for soldering or gluing to contacts on a printed circuit board for electrical connection to an electrical component such as an IC chip connected to the circuit traces on the substrate.