Abstract: An embodiment of an image processing apparatus may comprise one or more processors, memory coupled to the one or more processor to store image and mask data, and logic coupled to the one or more processors and the memory, the logic to capture a volumetric broadcast video signal in real-time and generate a sequence of frame images from the captured real-time volumetric broadcast video signal, segment an input image, which corresponds to a single frame of the sequence of frame images, to generate a mask image associated with the input image, and determine a mask quality score based on the input image and the associated mask image in real-time. Other embodiments are disclosed and claimed.

Abstract: An embodiment of an image processing apparatus may comprise one or more processors, memory coupled to the one or more processor to store image and mask data, and logic coupled to the one or more processors and the memory, the logic to capture a volumetric broadcast video signal in real-time and generate a sequence of frame images from the captured real-time volumetric broadcast video signal, segment an input image, which corresponds to a single frame of the sequence of frame images, to generate a mask image associated with the input image, and determine a mask quality score based on the input image and the associated mask image in real-time. Other embodiments are disclosed and claimed.

Abstract: An embodiment of mask quality predication technology may include a memory to store a set of input images and a reference mask image associated with each input image of the set of input images, a processor communicatively coupled to the memory, and logic communicatively coupled to the processor and the memory to generate a set of two or more masks of different quality associated with each input image of the set of input images, and determine a quality score for each generated mask. Other embodiments are disclosed and claimed.

Abstract: An embodiment of mask quality predication technology may include a memory to store a set of input images and a reference mask image associated with each input image of the set of input images, a processor communicatively coupled to the memory, and logic communicatively coupled to the processor and the memory to generate a set of two or more masks of different quality associated with each input image of the set of input images, and determine a quality score for each generated mask. Other embodiments are disclosed and claimed.

Abstract: A multiprocessor computing system includes a serial bus and implements a boot protocol in which each processor compares a vector field of a boot message issued on the serial bus by a first processor with an ID of the processor; a match indicating that the first processor is a bootstrap processor (BSP). The non-BSPs are halted and, after issuing a final message on the bus, the BSP fetches code to start a reset sequence. The BSP then sends a message to wake the non-BSPs, after which time the operating system software is given control. Faulty processors that fail to participate in the boot protocol do not stop the selection of a BSP as long as one processor in the system is functional.

Abstract: A multi-processor system that supports multiple programmable interrupt controllers (PIC). An advanced programmable interrupt controller (APIC) provides interface between the processors and the PICs. The APIC provides interface between processors and other I/O devices also. The APIC sends an interrupt request data packet with a first field set to a processor identification number, a second field set to a type of the device that sent interrupt request and a third field. The third field is set to an interrupt vector if the device sending the interrupt request to the APIC is a device other than PIC. The third field is set to a predetermined identification number of the PIC if the interrupt request is from the PIC. A processor, to which the interrupt is directed to, receives the packet. If the interrupt request is from a PIC, the processor uses the third field to identify which of the multiple PICs caused the interrupt.