Abstract: This invention relates to a ceramic module and to methods for forming protruding, upstanding electrically conducting pins by the selective abrasion of a surface 18 of a multilayered ceramic module 10. An abrasive blasting device 40 is disposed adjacent to the surface 18 for directing a stream of abrasive particles 42 against the surface. The particles 42 strike both metallic conductors 20 and 22 and also the ceramic material of the layer 14. Inasmuch as the ceramic material is relatively hard and brittle as compared to the ductile metallic conductors the abrasive particles 42 abrade away the ceramic layer 14 at a faster rate than the ductile metallic material of the conductors 20 and 22. The abrasive particles 42 may be comprised of any suitable abrasive, such as Al.sub.2 O.sub.3, SiC or WC. The module may be rotated beneath a nozzle of the grit blasting device, the nozzle being linearly translated above the surface being abraded.

Abstract: This invention relates to a ceramic module and to methods for forming protruding, upstanding electrically conducting pins by the selective abrasion of a surface 18 of a multilayered ceramic module 10. An abrasive blasting device 40 is disposed adjacent to the surface 18 for directing a stream of abrasive particles 42 against the surface. The particles 42 strike both metallic conductors 20 and 22 and also the ceramic material of the layer 14. Inasmuch as the ceramic material is relatively hard and brittle as compared to the ductile metallic conductors the abrasive particles 42 abrade away the ceramic layer 14 at a faster rate than the ductile metallic material of the conductors 20 and 22. The abrasive particles 42 may be comprised of any suitable abrasive, such as Al.sub.2 O.sub.3, SiC or WC. The module may be rotated beneath a nozzle of the grit blasting device, the nozzle being linearly translated above the surface being abraded.

Abstract: Balancing values of physical parameters such as temperature between used and unused circuit islands, in a fault bypass wafer circuit module, is done by mandating circuit exercise within each island considered critical. Within individual exercise islands, thermostats control heaters, or other physical parameter reporting means control transducers to return the physical parameter to nominal values. Heavily exercised operational islands and unexercised faulty or good redundant islands, which could develop destructive thermal gradients and resulting operational or connection failures. To eliminate such physical gradients, circuit exercise is mandated in all circuit islands which receive no ordinary circuit exercise, simply to maintain physical balance. Temperature is the physical parameter of primary concern, but physical parameters include piezoelectric effects, capacitance, inductance, magnetism, radiation effects and voltage, as well as other physical parameters which may be related or derivative.

Abstract: A modular system comprising a microprocessor having a system bus (control address and data) and one or more programmed logic arrays connected to said system bus. Three system configurations are shown by way of example, Macroprocessor, Peripheral Input/Output and Direct Memory Access applications. The microprocessor executes a standard set of instructions and addresses each programmed logic array. Each array executes a specific instruction, beyond the standard set of instructions, upon receipt of its address.

Abstract: This specification describes a set of arrays for performing logic function in various subsets of the original set. The array structure is characterized by a plurality of arrays joined together with a bidirectional bussing system. This bussing system comprises addressing lines of the arrays joined together by switching circuitry used to regroup the set into subsets as necessary to perform the logic functions.

Abstract: A system that is to be placed on a wafer is partitioned into reasonably large functions, each provided with a set of I/O and power pads. The wafer design is called "design A"0 A second wafer design (design B) that is the mirror image of design A is also constructed. Wafers of designs A and B are tested and divided into two groups: group I wafers have relatively few functions that are inoperative; group II wafers have relatively few functions that are operative. Inoperative functions are removed from group I wafers and discarded; good functions are removed from group II wafers and retained. A given function on wafer A is the mirror image of the same function on wafer B. Therefore, a given function from a group II wafer A (or B) can be inverted and attached to a group I wafer B (or A) that has had the corresponding function removed from it. The I/O and power pads of the function removed from the group II wafer are joined to the I/O and power pads remaining on the group I wafer.