Abstract: A memory transistor includes a body of semiconductor material having therein a channel region of one conductivity type and source and drain regions of the opposite conductivity type. A channel insulation is on the surface of the semiconductor body and extends over the channel region. The channel insulation includes a first layer of silicon dioxide directly on the surface of the semiconductor body and a layer of silicon nitride on the silicon dioxide layer. A gate of conductive polycrystalline silicon is preferable provided on the channel insulation. The channel of the transistor is sufficiently narrow so that electrons can be avalanched into the interface between the silicon nitride layer and the silicon dioxide layer completely across the full width of the channel where the electrons can be stored.

Abstract: A method for fabricating a submicron short channel MOS device is described wherein a plural or multilevel insulator layer, having a thickness of about 100-200 angstroms, is interposed between the polycrystalline silicon gate member and the substrate to function as a gate insulator and in addition, serving to protect the body of the semiconductor from becoming inadvertently doped during the processing steps.