Patents by Inventor Joseph Daniel Mis

Joseph Daniel Mis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6389691
    Abstract: A method for forming routing conductors and solder bumps on a microelectronic substrate includes the steps of forming an under bump metallurgy layer on the substrate and forming a solder structure on the under bump metallurgy layer where the solder structure includes an elongate portion and an enlarged width portion. The portions of the under bump metallurgy layer not covered by the solder structure can be selectively removed using the solder structure as a mask. In addition, the solder is caused to flow from the elongate portion of the solder structure to the enlarged width solder portion thereby forming a raised solder bump. This step is preferably performed by heating the solder structure above its liquidus temperature allowing surface tension induced internal pressures to affect the flow. Various solder structures are also disclosed.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: May 21, 2002
    Assignee: Unitive International Limited
    Inventors: Glenn A. Rinne, Joseph Daniel Mis
  • Patent number: 6329608
    Abstract: A flip-ship structure having a semiconductor substrate including an electronic device formed thereon, a contact pad on said semiconductor substrate electrically connected to said electronic device, a passivation layer on said semiconductor substrate and on said contact pad wherein said passivation layer defines a contact hole therein exposing a portion of said contact pad, an under-bump metallurgy structure on said passivation layer electrically contacting said portion of said contact pad that is exposed; and a solder structure on said under-bump metallurgy structure opposite said semiconductor substrate, said solder structure including an elongate portion on said elongate portion of said metallurgy structure opposite said contact pad and an enlarged width portion on said enlarged width portion of said metallurgy structure opposite said passivation layer.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: December 11, 2001
    Assignee: Unitive International Limited
    Inventors: Glenn A. Rinne, Joseph Daniel Mis
  • Patent number: 6222279
    Abstract: A method for fabricating solder bumps on a microelectronic device having contact pads includes the steps of depositing a titanium barrier layer on the device, forming an under bump metallurgy layer on the titanium barrier layer, and forming one or more solder bumps on the under bump metallurgy layer. The solder bump or bumps define exposed portions of the under bump metallurgy layer which are removed, and then the exposed portion of the titanium barrier layer is removed. The titanium barrier layer protects the underlying microelectronic device from the etchants used to remove the under bump metallurgy layer. The titanium layer also prevents the under bump metallurgy layer from forming a residue on the underlying microelectronic device. Accordingly, the titanium barrier layer allows the under bump metallurgy layer to be quickly removed without leaving residual matter thereby reducing the possibility of electrical shorts between solder bumps.
    Type: Grant
    Filed: April 20, 1998
    Date of Patent: April 24, 2001
    Assignee: MCNC
    Inventors: Joseph Daniel Mis, Gretchen Maerker Adema, Mark D. Kellam, W. Boyd Rogers
  • Patent number: 5902686
    Abstract: Method for forming a solder bump on a substrate include the steps of forming an under bump metallurgy layer on a substrate, forming a solder bump on the under bump metallurgy layer, and forming an intermetallic portion of the under bump metallurgy layer adjacent the solder bump. In particular, the solder bump has a predetermined shape and this predetermined shape is retained while forming the intermetallic portion of the under bump metallurgy layer. This predetermined shape preferably has a flat surface opposite the substrate thus providing a uniform thickness of solder during the formation of the intermetallic portion. Related structures are also disclosed.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: May 11, 1999
    Assignee: MCNC
    Inventor: Joseph Daniel Mis
  • Patent number: 5892179
    Abstract: A solder bump structure on a microelectronic substrate including an electrical contact having an exposed portion. This solder bump structure includes an under bump metallurgy structure on the microelectronic substrate, and a solder structure on the under bump metallurgy structure opposite the microelectronic substrate. The metallurgy structure includes an elongate portion having a first end which electronically contacts the exposed portion of the electrical contact and an enlarged width portion connected to a second end of the elongate portion. The solder structure includes an elongate portion on the metallurgy structure and an enlarged width portion on the enlarged width portion of the metallurgy structure. Accordingly, the enlarged width portion of the solder structure can be formed on a portion of the microelectronic substrate other than the contact pad and still be electronically connected to the pad.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: April 6, 1999
    Assignee: MCNC
    Inventors: Glenn A. Rinne, Joseph Daniel Mis
  • Patent number: 5767010
    Abstract: A method for fabricating solder bumps on a microelectronic device having contact pads includes the steps of depositing a titanium barrier layer on the device, forming an under bump metallurgy layer on the titanium barrier layer, and forming one or more solder bumps on the under bump metallurgy layer. The solder bump or bumps define exposed portions of the under bump metallurgy layer which are removed, and then the exposed portion of the titanium barrier layer is removed. The titanium barrier layer protects the underlying microelectronic device from the etchants used to remove the under bump metallurgy layer. The titanium layer also prevents the under bump metallurgy layer from forming a residue on the underlying microelectronic device. Accordingly, the titanium barrier layer allows the under bump metallurgy layer to be quickly removed without leaving residual matter thereby reducing the possibility of electrical shorts between solder bumps.
    Type: Grant
    Filed: November 5, 1996
    Date of Patent: June 16, 1998
    Assignee: MCNC
    Inventors: Joseph Daniel Mis, Gretchen Maerker Adema, Mark D. Kellam, W. Boyd Rogers