Abstract: A method of fabricating self-aligned static induction transistors is disclosed. The method comprises fabricating a silicon substrate having an active area. A guard ring is formed around the active area. Source and gate regions are formed, and a self-aligned relatively deep trench in accordance with the present invention is formed over the gate regions. This is achieved by forming an oxide layer, and forming a polysilicon layer on the oxide layer. A second oxide layer is formed on the polysilicon layer which is then masked by a self-aligning mask. Trenches are etched into the source and gate regions using the self-aligning mask and gate regions are formed at the bottom of the trenches. The transistors are then processed to completion by forming gate, source and drain regions.

Abstract: A solid state triode employs the Hall effect to asymmetrically proportion flow of current through different branches of a number of cascaded bifurcated N- charge carrier channels (10,18,20), thereby providing an indication of strength and direction of an applied magnetic field by measuring magnitude and sense of the difference between currents flowing in the two channel branches (14,16,24,26,30,32). The solid state triode is formed on an silicon-on-insulator (SOI) substrate (47,48,49) in which an N+ source region (54) and at least two end N+ drain regions (56,58) are interconnected by an N- charge carrier channel (60) that is defined by a plurality of P+ regions (64a,64b,64c,64d) in a thin single crystal silicon substrate (49) between the source and drain regions (54,56,58). A polysilicon gate (52) overlies the N- channel and acts as a self-aligning mask during manufacture of the triode to precisely align the N+ and P+ doping to the polysilicon gate configuration.

Abstract: A polysilicon gate (42) of an N-channel MOSFET (40) includes a P+ doped central portion (42a), and N+ doped lateral portions (42b,42c) which face an N-type source (24c) and drain (26c) respectively. An N-type dopant is implanted into the surface portion of a P-type channel region (18) to reduce the surface doping and adjust the transistor threshold voltage to approximately 0.8 volts. The lowered channel doping reduces the electric field at the drain (26c) and suppresses injection of hot electrons from the drain (26c) into the gate oxide (14), and also reduces the electric field across the gate oxide (14) and suppresses charging thereof by hot electrons.

Abstract: Each unit cell (10) of a flash EEPROM array (50) includes a source (18), a drain (20) and a channel (22) formed in a substrate (12). A thin tunnel oxide layer (32) is formed over the substrate (12) and P-Well (14). A bifurcated floating gate (34) is formed on the tunnel oxide layer (32) overlying the channel (22) , and includes a program arm (34a) which overlaps the drain (20), an erase arm (34b) which overlaps the source (18) and a base (34c) which extends around an end of the channel (22) and interconnects the program and erase arms (34a,34b). A thick gate oxide layer (36,36a) is formed over the floating gate (34), and a control gate (38) is formed over the gate oxide layer (36,36a). A central section of the control gate (38) which overlies a gap (34d) between the program and erase arms (34a, 34b) provides threshold voltage control for erasure. The erase arm (34b) spans the entire width of the channel (22), enabling erasure with low applied voltages.

Abstract: A polysilicon gate (42) of an N-channel MOSFET (40) includes a P+ doped central portion (42a), and N+ doped lateral portions (42b,42c) which face an N-type source (24c) and drain (26c) respectively. An N-type dopant is implanted into the surface portion of a P-type channel region (18) to reduce the surface doping and adjust the transistor threshold voltage to approximately 0.8 volts. The lowered channel doping reduces the electric field at the drain (26c) and suppresses injection of hot electrons from the drain (26c) into the gate oxide (14), and also reduces the electric field across the gate oxide (14) and suppresses charging thereof by hot electrons.

Abstract: A method of fabricating self aligned static induction transistors. The method comprises fabricating an N silicon on N.sup.- silicon substrate having an active area. A guard ring is formed around the active area. An N.sup.+ polysilicon layer is formed that comprises source and gate regions. An oxide layer is formed on the N.sup.+ polysilicon layer. A second polysilicon layer is formed on the oxide layer. A second oxide layer is formed on the second polysilicon layer which is then masked by a self aligning mask. Trenches are etched into the substrate using the self aligning mask and gate regions are formed at the bottom of the trenches. A first layer of metal (gate metal) is deposited to make contact with the gate regions. A layer of photoresist is deposited and planarized, and the first layer of metal is overetched below the top surface of the trench. Plasma nitride is deposited and planarized, and a polysilicon mask is deposited over the planarized layer of plasma nitride.

Abstract: Complimentary metal oxide silicon transistors fabricated on silicon-on-insulator substrates are configured to allow separately controllable and independent backgate bias for adjacent complimentary devices on the same substrate. By means of deep implantation of boron, a backgate bias P- well (26,126) is positioned on the N-substrate (17,117) at a front surface of the N- substrate behind the N channel transistor of a complimentary pair. The backgate bias P- well (26,126) is provided with an electrical contact (48,148) at the front of the device, as is the N- silicon substrate to enable independent application of separate bias voltage of different polarities and appropriate magnitude.

Abstract: Methods of fabricating heavily doped edges of mesa structures in silicon-on-sapphire and silicon-on-insulator semiconductor devices. The methods are self-aligning and require a minimum of masking steps to achieve. The disclosed methods reduce edge leakage and resolve N-channel threshold voltage instability problems. Mesa structures are formed that comprise N-channel and P-channel regions having a thermal oxide layer deposited thereover. A doping layer of borosilicate glass, or alternatively, an undoped oxide layer that is subsequently implanted, is deposited over the mesa structures. In the first method, the doping layer is etched by means of an anisotropic plasma etching procedure to form oxide spacers at the edges of the mesa structures. The doping layer is removed from the N-mesa structures using an N-channel mask and wet oxide etching procedure. The structure is then heated to a relatively high temperature to drive the dopant into the edges of the N-channel mesa structures.

Abstract: A process for forming MOS devices having graded source and drain regions. The source and drain regions are lightly doped by ion implantation and then subjected to thermal cycling to diffuse the implanted impurities. The source and drain regions are then heavily doped to form source and drain regions having a heavily doped subregion and a lightly doped subregion. Devices made pursuant to the process, which can be made less than one-half micron, are not subject to gate oxide charging and have high snapback voltages.

Abstract: A process is disclosed for filling contact or via openings in an integrated circuit with electrically conductive plugs. The process includes the steps of (a) forming one or more openings in an planarized oxide layer, where the one or more openings is disposed over and exposes semi-insulating or conductive regions, and (b) filling the one or more openings with conductive material to substantially the same level as the adjacent surfaces of the oxide layer to form respective planarized conductive plugs.