Patents by Inventor Joseph E. Geusic
Joseph E. Geusic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7260125Abstract: A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped empty space patterns are formed by drilling holes in the substrate and annealing the substrate to form the spaced-apart plate-shaped empty space patterns.Type: GrantFiled: April 5, 2005Date of Patent: August 21, 2007Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Eugene P. Marsh
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Patent number: 7242049Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.Type: GrantFiled: June 11, 2003Date of Patent: July 10, 2007Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Joseph E. Geusic
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Patent number: 7196929Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.Type: GrantFiled: August 14, 1998Date of Patent: March 27, 2007Assignee: Micron Technology IncInventors: Leonard Forbes, Joseph E. Geusic, Kie Y. Ahn
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Patent number: 7169666Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.Type: GrantFiled: August 29, 2002Date of Patent: January 30, 2007Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Joseph E. Geusic
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Patent number: 7164156Abstract: An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.Type: GrantFiled: January 30, 2006Date of Patent: January 16, 2007Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Kie Y. Ahn, Leonard Forbes
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Patent number: 7154153Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.Type: GrantFiled: July 29, 1997Date of Patent: December 26, 2006Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Joseph E. Geusic
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Patent number: 7153775Abstract: A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first material (e.g., copper) while one or more portions of the second material (e.g., copper oxide) remain. One or more portions of the remaining second material (e.g., copper oxide) are removed selectively relative to converted portions of first material (e.g., copper). Further, a thickness of the converted portions may be increased. Yet further, a diffusion barrier layer may be used for certain applications.Type: GrantFiled: August 30, 2005Date of Patent: December 26, 2006Assignee: Micron Technology, Inc,Inventors: Joseph E. Geusic, Alan R. Reinberg
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Patent number: 7142577Abstract: A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped empty space patterns are formed by drilling holes in the substrate and annealing the substrate to form the spaced-apart plate-shaped empty space patterns.Type: GrantFiled: May 16, 2001Date of Patent: November 28, 2006Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Eugene P. Marsh
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Patent number: 7132348Abstract: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein.Type: GrantFiled: March 25, 2002Date of Patent: November 7, 2006Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Paul A. Farrar, Arup Bhattacharyya
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Patent number: 7109548Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.Type: GrantFiled: February 27, 2004Date of Patent: September 19, 2006Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Joseph E. Geusic
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Patent number: 7084067Abstract: An apparatus and a method for photoreducing copper oxide layers from semiconductor wafers during the processes of forming interconnects in advanced IC manufacturing. The apparatus comprises a reaction chamber with a high intensity UV light source and a wafer holder in the chamber. The UV light source is made of arrays of microdischarge devices fabricated on a semiconductor wafer where each of the microdischarge devices has the structure of a hollow cathode. Multiple arrays of microdischarge devices can be assembled together to make a planar UV lamp so as to provide a sufficient area for the UV illumination. The wafer holder in the chamber is made rotatable for a better uniformity during the photoreduction process. A non-oxidizing gas is flowed into the chamber to prevent instant and subsequent oxidation on the copper surface.Type: GrantFiled: March 31, 2003Date of Patent: August 1, 2006Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Alan R. Reinberg
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Patent number: 7084451Abstract: A method for forming a trench capacitor. The method includes forming a trench in a semiconductor substrate. A conformal layer of semiconductor material is deposited in the trench. The surface of the conformal layer of semiconductor material is roughened. An insulator layer is formed outwardly from the roughened, conformal layer of semiconductor material. A polycrystalline semiconductor plate is formed outwardly from the insulator layer in the trench.Type: GrantFiled: December 20, 1999Date of Patent: August 1, 2006Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Joseph E. Geusic, Kie Y. Ahn
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Patent number: 7054532Abstract: A waveguide structure formed with a three-dimensional (3D) photonic crystal is disclosed. The 3D photonic crystal comprises a periodic array of voids formed in a solid substrate. The voids are arranged to create a complete photonic bandgap. The voids maybe formed using a technique called “surface transformation,” which involves forming holes in the substrate surface, and annealing the substrate to initiate migration of the substrate near the surface to form voids in the substrate. A channel capable of transmitting radiation corresponding to the complete bandgap is formed in the 3D photonic crystal, thus forming the waveguide. The waveguide may be formed by interfacing two 3D photonic crystal regions, with at least one of the regions having a channel formed therein. The bandgap wavelength can be chosen by arranging the periodic array of voids to have a lattice constant a fraction of the bandgap wavelength.Type: GrantFiled: December 7, 2004Date of Patent: May 30, 2006Assignee: Micron Technoloy. Inc.Inventors: Leonard Forbes, Joseph E. Geusic
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Patent number: 7025646Abstract: A microcavity discharge device generates radiation with wavelengths in the range of from 11 to 14 nanometers. The device has a semiconductor plug, a dielectric layer, and an anode layer. A microcavity extends completely through the anode and dielectric layers and partially into the semiconductor plug. According to one aspect of the invention, a substrate layer has an aperture aligned with the microcavity. The microcavity is filled with a discharge gas under pressure which is excited by a combination of constant DC current and a pulsed current to produce radiation of the desired wavelength. The radiation is emitted through the base of the microcavity. A second embodiment has a metal layer which transmits radiation with wavelengths in the range of from 11 to 12 nanometers, and which excludes longer wavelengths from the emitted beam.Type: GrantFiled: June 13, 2005Date of Patent: April 11, 2006Assignee: Micron Technology, Inc.Inventor: Joseph E. Geusic
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Patent number: 7022604Abstract: A surface-transformation method of forming regions of a second material in a first solid material to control the properties of the first solid material is disclosed. The regions of the second material are formed in the first solid material by drilling holes to a predefined depth and at a predefined lattice position. The holes in the first solid material are then filled with a second material and then the first and second materials are heated to a temperature close to the melting point of the first solid material to spontaneously form the regions filled with the second material and embedded in the first solid material at the desired location. A liquid-phase immersion method or a deposition method may be employed to fill the holes in the first solid material.Type: GrantFiled: April 9, 2002Date of Patent: April 4, 2006Assignee: Micron Technology, Inc.Inventor: Joseph E. Geusic
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Patent number: 7018467Abstract: A method of forming a three-dimensional (3D) complete photonic bandgap crystal by crystal modification is disclosed. The 3D crystal includes a first periodic array of unit cells formed from first voids connected by imaginary bonds. The first periodic array forms an incomplete bandgap. The first voids may be formed in any one of a number of shapes, including spherical. The 3D crystal further includes a second periodic array of second voids. The second voids are arranged along the imaginary bonds so as to modify each unit cell. The modification of the unit cells is designed to form a complete photonic bandgap.Type: GrantFiled: January 17, 2002Date of Patent: March 28, 2006Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Leonard Forbes
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Patent number: 6998787Abstract: A microcavity discharge device generates radiation with wavelengths in the range of from 11 to 14 nanometers. The device has a semiconductor plug, a dielectric layer, and an anode layer. A microcavity extends completely through the anode and dielectric layers and partially into the semiconductor plug. According to one aspect of the invention, a substrate layer has an aperture aligned with the microcavity. The microcavity is filled with a discharge gas under pressure which is excited by a combination of constant DC current and a pulsed current to produce radiation of the desired wavelength. The radiation is emitted through the base of the microcavity. A second embodiment has a metal layer which transmits radiation with wavelengths in the range of from 11 to 12 nanometers, and which excludes longer wavelengths from the emitted beam.Type: GrantFiled: August 26, 2003Date of Patent: February 14, 2006Assignee: Micron Technology, Inc.Inventor: Joseph E. Geusic
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Patent number: 6995441Abstract: An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.Type: GrantFiled: May 8, 2003Date of Patent: February 7, 2006Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Kie Y. Ahn, Leonard Forbes
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Patent number: 6995443Abstract: An integrated circuit with a number of optical fibers that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical fibers include a cladding layer and a core formed in the high aspect ratio hole. These optical fibers are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.Type: GrantFiled: February 5, 2004Date of Patent: February 7, 2006Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Kie Y. Ahn, Leonard Forbes
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Patent number: 6979880Abstract: Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (keff) such that a programming pulse voltage is scalable with Vdd. One aspect of the present subject matter is an antifuse device that is positioned or coupled between a first metal level and a second metal level. One embodiment of the antifuse device includes a porous antifuse dielectric layer, and at least one injector Silicon-Rich-Insulator (SRI) layer in contact with the porous antifuse dielectric layer. In one embodiment, the porous antifuse dielectric layer includes SiO2 formed with air-filled voids. In one embodiment, the at least one injector SRI layer includes two injector Silicon-Rich-Nitride layers that sandwich the porous antifuse dielectric layer. Other aspects are provided herein.Type: GrantFiled: August 31, 2004Date of Patent: December 27, 2005Assignee: Micron Technology, Inc.Inventors: Arup Bhattacharyya, Joseph E. Geusic