Abstract: Techniques are disclosed herein for iceberg order processing by an exchange system that includes storing a first representation of an iceberg order requested by a user in an order book and automatically causing a second representation to be stored for the iceberg order in the order book after the displayed quantity associated with the first representation is depleted/zeroed or otherwise below a predetermined threshold following execution of an associated trade. The second representation of an iceberg order can be referred to as a reclip order, and N number of such reclip orders can be stored/accepted in this manner by the exchange system until a hidden/reserve quantity (also referred to herein as a remaining iceberg quantity) is zero or the user who originated the iceberg order submits a cancel request.

Abstract: Apparatus and a concomitant method for accessing an image pyramid that is sequentially stored in a memory. The invention uses an integer portion of the standard U, V, and D values that define a target pixel location within an image pyramid to determine a first address of a pixel value near the target location within the memory. From this first address, the invention determines another seven addresses. These eight addresses are used to recall pixel values that are proximate the target pixel location. These eight pixel values can then be used in a tri-linear interpolation to determine the target pixel value. The disclosed method and apparatus may find applicability in video servers, medical imaging, special effects and animation and location based entertainment systems among other applications.

Abstract: A processor within a parallel processing computer having a plurality of processors, where each processor is directly connected to a local storage memory. Each processor contains a principal processing element (PPE), a memory controller, and a multiplexor. The PPE executes a series of program instructions including local storage memory access instructions that cause the PPE to produce a local storage memory access request for accessing information within the local storage memory. The memory controller is connected to the PPE and a plurality of information resources of the parallel processing computer.

Abstract: A parallel computing system comprising N blocks of processors, where N is an integer greater than 1. Each block of the N blocks of processors contains M processors, where M is an integer greater than 1. Each processor includes an arithmetic logic unit (ALU), a local memory and an input/output (I/O) interface. The computing system also contains a control means, connected to each of the M processors, for providing identical instructions to each of the M processors, and a host means, coupled to each of the control means within the N blocks of processors. The host means selectively organizes the control means of each of the N blocks of M processors into at least two groups of P blocks of M processors, P being an integer less than or equal to N. In operation, the host means causes the control means within each group of P blocks of M processors to provide each group of P blocks of M processors respectively different identical processor instructions.

Abstract: A processor for use in a parallel computing system. The processor contains: a memory for storing operand values; an arithmetic logic unit (ALU) for performing arithmetic logic operations on operand values; a multiplier, separate from the ALU and coupled to the memory, for generating arithmetic products of a first operand value and a second operand values; and a match unit, separate from the ALU and coupled to the memory, for detecting matches between a predetermined bit pattern and a sequence of bits retrieved from the memory. The match unit also generates a count value indicating a number of detected matches between the predetermined bit pattern and subsequences of bits within the sequence of bits. The first operand value contains the bit pattern and the second operand contains the sequence of bits.