Patents by Inventor Joseph E. Simko

Joseph E. Simko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7626845
    Abstract: In one embodiment, the invention is an integrated circuit (IC) including an OTP memory and conditioning circuitry. The IC receives an externally-generated DC programming voltage signal that the conditioning circuitry transforms into a programming pulse signal for programming the OTP memory. The conditioning circuitry includes: (i) reset protection circuitry for holding the programming pulse signal low if the IC is powering up, (ii) an overvoltage protection circuit for substantially preventing the programming pulse voltage from exceeding predefined boundaries, and (iii) a conversion switch for controlling the programming pulse voltage. The programming pulse voltage is (i) substantially equivalent to the externally-generated DC voltage if an enable signal is on, and (ii) substantially equivalent to a reference voltage if the enable signal is off.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: December 1, 2009
    Assignee: Agere Systems Inc.
    Inventors: Clinton H. Holder, Jr., Kang W. Lee, Joseph E. Simko, Yehuda Smooha, Ying Zhu
  • Patent number: 7397279
    Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp circuit is connected between the input stage and the latch circuit. The voltage clamp circuit is operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: July 8, 2008
    Assignee: Agere Systems Inc.
    Inventors: Dipankar Bhattacharya, Makeshwar Kothandaraman, John C. Kriz, Bernard L. Morris, Joseph E. Simko
  • Publication number: 20080144350
    Abstract: In one embodiment, the invention is an integrated circuit (IC) including an OTP memory and conditioning circuitry. The IC receives an externally-generated DC programming voltage signal that the conditioning circuitry transforms into a programming pulse signal for programming the OTP memory. The conditioning circuitry includes: (i) reset protection circuitry for holding the programming pulse signal low if the IC is powering up, (ii) an overvoltage protection circuit for substantially preventing the programming pulse voltage from exceeding predefined boundaries, and (iii) a conversion switch for controlling the programming pulse voltage. The programming pulse voltage is (i) substantially equivalent to the externally-generated DC voltage if an enable signal is on, and (ii) substantially equivalent to a reference voltage if the enable signal is off.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 19, 2008
    Applicant: AGERE SYSTEMS INC.
    Inventors: Clinton H. Holder, Kang W. Lee, Joseph E. Simko, Yehuda Smooha, Ying Zhu
  • Patent number: 7034653
    Abstract: A semiconductor resistor comprises a resistor body formed on a semiconductor substrate and first and second conductive terminals electrically connected to the resistor body at opposite ends thereof. The semiconductor resistor further includes at least first and second conductive paths between at least one of the first and second conductive terminals and the resistor body. The at least one conductive terminal is configured such that a resistance of the at least one conductive terminal between the at least first and second conductive paths is substantially matched to a resistance of the resistor body between the at least first and second conductive paths. In this manner, a current distribution between the at least first and second conductive paths is substantially matched.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: April 25, 2006
    Assignee: Agere Systems Inc.
    Inventors: Dipankar Bhattacharya, John Christopher Kriz, Stefan Allen Siegel, Joseph E. Simko, Yehuda Smooha
  • Patent number: 6992489
    Abstract: A circuit configurable for indicating a voltage level of an input signal applied to the circuit includes at least one transistor having a first terminal connected to a first voltage supply, a second terminal configured for receiving the input signal, and a third terminal operatively coupled to an output of the circuit. The circuit further includes a passive load connected between the third terminal of the transistor and a second voltage supply. The circuit is configured to generate an output signal at the output of the circuit. The output signal being at a first value indicates that the input signal is substantially at a first voltage level, and the output signal being at a second value indicates that the input signal is substantially at a second voltage level.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: January 31, 2006
    Assignee: Agere Systems Inc.
    Inventors: Dipankar Bhattacharya, John Christopher Kriz, Joseph E. Simko