Abstract: In an optical fiber telecommunications network, an optical network unit is provided in the subscriber neighborhood for terminating the optical fiber transmission line and for providing electrical signals over metallic lines to the subscribers. The unit functions to convert the optical signal to an electrical signal and demultiplex the electrical signal to divide out baseband telephony signals from broadband video channels. The electrical signals are further demultiplexed and distributed to line cards serving each subscriber, while the broadband video channels are demultiplexed and provided to subscribers that have requested specific video channels. The system includes a test unit for performing metallic tests and also a means to gather subscriber channel requests to form a video control channel which is transmitted to a remote terminal via a baseband telephony channel.

Abstract: In fiber telecommunications network where an optical fiber is extended to the subscriber's neighborhood, mechanized loop testing is performed by a test unit located in a network unit in the subscriber's neighborhood. The test unit is responsive to commands from a controller located in the network unit to perform metallic line tests on the lines extending to the subscriber. Test results are stored in a memory associated with the controller in the network unit. Upon receipt of a test request from a central test controller, the controller within the network unit determines if there is sufficient time to perform the test; if so, a new test is performed and the results are conveyed back to the central test controller controller. If sufficient time is not available, the results of the last performed routine test contained in the memory are transmitted back to the central test controller.

Abstract: In an optical fiber telecommunication transmission system, a remote terminal interfaces a high-rate optical fiber feeder line and a plurality of lower rate optical fiber distribution lines. The remote terminal includes a plurality of interfacing and signal cross-connecting devices which interface and cross-connect lower rate telephony signals with higher rate telephony signals. The plurality of interfacing and cross-connecting devices are interconnected with high-rate transmission lines so that telephony signals from under-utilized optical fiber distribution lines may be concentrated onto the high-rate optical fiber feeder line for efficient use of the feeder line.

Abstract: In an integrated telecommunications network adapted to provide narrowband telephony signals and broadband switched video signals, control signals for the broadband video signals are transmitted in the narrowband as baseband signals, which are frequency division multiplexed with the broadband switched video signals. The video control signals are transmitted over the same transmission lines as the broadband video signals and do not require the installation of additional transmission lines. Control signals from a plurality of subscribers are multiplexed together at a network unit and are transmitted as a channel on an optical fiber, after which the channels from a plurality of network units are further multiplexed together to form a frame of control channels which are transmitted to a video controller unit.

Abstract: A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

Abstract: A video line shelf arrangement allows for incremental growth in video channels provided to optical network units. The arrangement includes a number of video line shelves disposed vertically in a column. Each video line shelf includes a number of slots, with the slots of adjacent shelves being aligned vertically. Video line cards each providing six video channels are inserted into selected slots of the video line shelf, as are necessary to provide the required number of channels. A vertical column of video line cards is arranged to service a single optical network unit. Thus, only the necessary number of video line cards are inserted into the slots aligned in a column serving a single optical network unit.

Abstract: A terminal for a telecommunications system provides access to one or two high-speed synchronous transmission lines by both low-speed transmission lines and subscriber lines. A core module includes interfaces to the high-speed lines, a time slot interchanger, an interface to the low-speed transmission lines, processors and overhead circuitry for supporting the terminal. An access module includes a plurality of line shelves connected to subscriber lines, each line shelf includes a pair of processors and for time slot assignors. A multi-link serial bus connects the time slot interchanger to the access module and to the low-speed interface and provides close coupling between the processors in the core module and the line shelves. The processors cooperate to groom subscriber information from said subscriber lines to and from time slots in said high-speed feeder line and said low-speed transmission line.

Abstract: A three-ported apparatus is adapted to interface a serial TDM bus, a local controller and a line unit bus in a telecommunications terminal. All data passing between the TDM bus and the line unit bus is temporarily stored and is accessible to the local controller, allowing the controller to either pass said data without modification or provide modifications thereto. Signaling contained within the data may be translated to a form usable by the line unit through the use of translation tables down-loaded from inventory storage on the line units. For each line unit, the local controller programmably controls time slot assignment, provisioning and inventory information access.

Abstract: A parallel time slot interchanger, particularly for use in telecommunication switching, comprises a plurality of switch groups, with each switch group containing a second plurality of channels. The parallel time slot interchanger incroporated a matrix-type architecture, with each module of the matrix comprising a switch block which in turn incorporates a switch memory, connect memory and associated control circuitry. The connect memory of each switch block is controlled by the control circuitry of that block. The data stored in the connect memory contains switch memory address information for reading channel data stored within the switch memory of the same switch block so as to be able to perform a time slot switching function during any given time slot of the parallel time slot interchanger. Each switch block is uniquely identified within its corresponding switch group so that only one switch memory address location is read and output during any time slot for each switch group.

Abstract: A line unit interface circuit used on line units in a line shelf of a digital loop carrier provides all of the logic necessary to access two subscriber lines to a line unit interface bus connected to common equipment within the line shelf. Information received from the common equipment includes signaling data, configuration data and provisioning data, which is reconfigured and processed by the line unit interface circuit for controlling the subscriber line channels. Configuration data from the common equipment is decoded to assign time slots on the line unit interface bus to the various channels serviced by the line shelf and to further provide for a timing offset between the transmit and receive strobes provided to each subscriber line circuit. A flywheel circuit is used to prevent erroneous time slot assignment in the event of noise or interference on the line unit interface bus.

Abstract: A digital debouncing and storage apparatus operates on the receiving end of a digital carrier span line used in a telephony system to couple a multiplex signal to a receiving site to be used by the switching network control. Incoming signaling bits of the multiplex signal are stored in a random access memory at a particular storage location reserved for each channel contained in a group. There is also stored at the location previous timing information concerning each sampling bit. The circuit operates to time any change in the value of a status bit to insure that it lasts long enough to indicate a valid change of state. An up/down counter serves to time each status bit during predetermined signaling frames based on a count inserted into the counter indicative of the timing information as stored in memory. Thus each channel associated with the multiplex signal has stored in memory a unique status bit as well as timing information pertinent to that bit.

Abstract: An elastic storage circuit employs a first in/first out (FIFO) memory which stores data contained in a serial stream in a plurality of locations, each of which is associated with a unique address. The storage locations operate to store both the data and the address. A word address counter generates a five bit address code to accompany the data bits as stored in the FIFO. If a chronic increase or decrease in the frequency rate of the data occurs, the FIFO will overflow or underflow. This condition is detected by suitable detectors which create an alarm to completely reset the entire contents of the memory and to refill a portion of the memory over a given interval sufficient to permit the system to recover from the slip in the data rate and to thereafter synchronously read the data together with the address identification from the FIFO.