Patents by Inventor Joseph Gerald McDonald
Joseph Gerald McDonald has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11550723Abstract: An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.Type: GrantFiled: August 27, 2018Date of Patent: January 10, 2023Assignee: Qualcomm IncorporatedInventors: Niket Choudhary, David Scott Ray, Thomas Philip Speier, Eric Robinson, Harold Wade Cain, III, Nikhil Narendradev Sharma, Joseph Gerald McDonald, Brian Michael Stempel, Garrett Michael Drapala
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Patent number: 11226910Abstract: Disclosed are ticketed flow control mechanisms in a processing system with one or more masters and one or more slaves. In an aspect, a targeted slave receives a request from a requesting master. If the targeted slave is unavailable to service the request, a ticket for the request is provided to the requesting master. As resources in the targeted slave become available, messages are broadcasted for the requesting master to update the ticket value. When the ticket value has been updated to a final value, the requesting master may re-transmit the request.Type: GrantFiled: March 3, 2020Date of Patent: January 18, 2022Assignee: Qualcomm IncorporatedInventors: Joseph Gerald McDonald, Garrett Michael Drapala, Eric Francis Robinson, Thomas Philip Speier, Kevin Neal Magill, Richard Gerard Hofmann
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Patent number: 11016899Abstract: Selective honoring of speculative memory-prefetch requests based on bandwidth constraint of a memory access path component(s) in a processor-based system. To reduce memory access latency, a CPU includes a request size in a memory read request of requested data to be read from memory and a request mode of the requested data as required or preferred. A memory access path component includes a memory read honor circuit configured to receive the memory read request and consult the request size and request mode of requested data in the memory read request. If the selective prefetch data honor circuit determines that bandwidth of the memory system is less than a defined bandwidth constraint threshold, then the memory read request is forwarded to be fulfilled, otherwise, the memory read request is downgraded to only include any requested required data.Type: GrantFiled: May 6, 2019Date of Patent: May 25, 2021Assignee: Qualcomm IncorporatedInventors: Nikhil Narendradev Sharma, Eric Francis Robinson, Garrett Michael Drapala, Perry Willmann Remaklus, Jr., Joseph Gerald McDonald, Thomas Philip Speier
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Publication number: 20200356486Abstract: Selective honoring of speculative memory-prefetch requests based on bandwidth constraint of a memory access path component(s) in a processor-based system. To reduce memory access latency, a CPU includes a request size in a memory read request of requested data to be read from memory and a request mode of the requested data as required or preferred. A memory access path component includes a memory read honor circuit configured to receive the memory read request and consult the request size and request mode of requested data in the memory read request. If the selective prefetch data honor circuit determines that bandwidth of the memory system is less than a defined bandwidth constraint threshold, then the memory read request is forwarded to be fulfilled, otherwise, the memory read request is downgraded to only include any requested required data.Type: ApplicationFiled: May 6, 2019Publication date: November 12, 2020Inventors: Nikhil Narendradev Sharma, Eric Francis Robinson, Garrett Michael Drapala, Perry Willmann Remaklus, JR., Joseph Gerald McDonald, Thomas Philip Speier
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Publication number: 20200285597Abstract: Disclosed are ticketed flow control mechanisms in a processing system with one or more masters and one or more slaves. In an aspect, a targeted slave receives a request from a requesting master. If the targeted slave is unavailable to service the request, a ticket for the request is provided to the requesting master. As resources in the targeted slave become available, messages are broadcasted for the requesting master to update the ticket value. When the ticket value has been updated to a final value, the requesting master may re-transmit the request.Type: ApplicationFiled: March 3, 2020Publication date: September 10, 2020Inventors: Joseph Gerald MCDONALD, Garrett Michael DRAPALA, Eric Francis ROBINSON, Thomas Philip SPEIER, Kevin Neal MAGILL, Richard Gerard HOFMANN
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Publication number: 20200065247Abstract: An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.Type: ApplicationFiled: August 27, 2018Publication date: February 27, 2020Inventors: Niket CHOUDHARY, David Scott RAY, Thomas Philip SPEIER, Eric ROBINSON, Harold Wade CAIN, III, Nikhil Narendradev SHARMA, Joseph Gerald MCDONALD, Brian Michael STEMPEL, Garrett Michael DRAPALA
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Publication number: 20190087333Abstract: Converting a stale cache memory unique request to a read unique snoop response in a multiple (multi-) central processing unit (CPU) processor is disclosed. The multi-CPU processor includes a plurality of CPUs that each have access to either private or shared cache memories in a cache memory system. Multiple CPUs issuing unique requests to write data to a same coherence granule in a cache memory causes one unique request for a requested CPU to be serviced or “win” to allow that CPU to obtain the coherence granule in a unique state, while the other unsuccessful unique requests become stale. To avoid retried unique requests being reordered behind other pending, younger requests which would lead to lack of forward progress due to starvation or livelock, the snooped stale unique requests are converted to read unique snoop responses so that their request order can be maintained in the cache memory system.Type: ApplicationFiled: September 12, 2018Publication date: March 21, 2019Inventors: Eric Francis Robinson, Thomas Philip Speier, Joseph Gerald McDonald, Garrett Michael Drapala, Kevin Neal Magill
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Publication number: 20190012265Abstract: Providing multi-socket memory coherency using cross-socket snoop filtering in processor-based systems is disclosed. In this regard, a processor-based system provides a plurality of processor sockets, each associated with a coherency directory including a plurality of coherency directory entries each storing status indicators corresponding to memory granules of a local memory hierarchy. A point of serialization (POS) circuit of the processor-based system receives a memory access request including a local memory address, and retrieves a coherency directory entry corresponding to the local memory address. If a status indicator of the coherency directory entry corresponding to a memory granule associated with the local memory address indicates that a remote snoop is required, the POS circuit performs the remote snoop of one or more remote processor sockets indicated by the status indicator. If not, the POS circuit returns data from the local memory hierarchy for the memory access request.Type: ApplicationFiled: July 6, 2017Publication date: January 10, 2019Inventors: Robert James Safranek, Joseph Gerald McDonald, Robert Likovich, JR., Satish Srerambatla
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Patent number: 9594713Abstract: Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media are disclosed. In one aspect, a host bridge device is configured to receive strongly ordered write transactions from one or more strongly ordered producer devices. The host bridge device issues the strongly ordered write transactions to one or more consumer devices within a weakly ordered domain. The host bridge device detects a first write transaction that is not accepted by a first consumer device of the one or more consumer devices. For each of one or more write transactions issued subsequent to the first write transaction and accepted by a respective consumer device, the host bridge device sends a cancellation message to the respective consumer device. The host bridge device replays the first write transaction and the one or more write transactions that were issued subsequent to the first write transaction.Type: GrantFiled: September 12, 2014Date of Patent: March 14, 2017Assignee: QUALCOMM IncorporatedInventors: Randall John Pascarella, Jaya Prakash Subramaniam Ganasan, Thuong Quang Truong, Gurushankar Rajamani, Joseph Gerald McDonald, Thomas Philip Speier
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Patent number: 9448846Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.Type: GrantFiled: December 13, 2011Date of Patent: September 20, 2016Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Bartholomew Blaner, George William Daly, Jr., Jeffrey Haskell Derby, Ross Boyd Leavens, Joseph Gerald McDonald
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Publication number: 20160077991Abstract: Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media are disclosed. In one aspect, a host bridge device is configured to receive strongly ordered write transactions from one or more strongly ordered producer devices. The host bridge device issues the strongly ordered write transactions to one or more consumer devices within a weakly ordered domain. The host bridge device detects a first write transaction that is not accepted by a first consumer device of the one or more consumer devices. For each of one or more write transactions issued subsequent to the first write transaction and accepted by a respective consumer device, the host bridge device sends a cancellation message to the respective consumer device. The host bridge device replays the first write transaction and the one or more write transactions that were issued subsequent to the first write transaction.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Randall John Pascarella, Jaya Prakash Subramaniam Ganasan, Thuong Quang Truong, Gurushankar Rajamani, Joseph Gerald McDonald, Thomas Philip Speier
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Publication number: 20130152099Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Applicant: International Business Machines CorporationInventors: Brian Mitchell Bass, Bartholomew Blaner, George William Daly, JR., Jeffrey Haskell Derby, Ross Boyd Leavens, Joseph Gerald McDonald
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Patent number: 8230117Abstract: A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.Type: GrantFiled: April 9, 2009Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: George William Daly, Jr., Guy Lynn Guthrie, Ross Boyd Leavens, Joseph Gerald McDonald, Michael Steven Siegel, William John Starke, Derek Edward Williams
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Publication number: 20100262720Abstract: A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.Type: ApplicationFiled: April 9, 2009Publication date: October 14, 2010Applicant: INTERNATIONAL BUISNESS MACHINES CORPORATIONInventors: George William Daly, JR., Guy Lynn Guthrie, Ross Boyd Leavens, Joseph Gerald McDonald, Michael Steven Siegel, William John Starke, Derek Edward Williams
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Patent number: 6618357Abstract: In pause time based flow control systems having station-level granularity, a station or switch may detect congestion or incipient congestion and send a flow control frame to an upstream station, commanding that upstream station to temporarily stop (pause) sending data for a period of time specified in the flow control frame. The traffic pause gives the downstream station time to empty its buffers of at least some of the excess traffic it has been receiving. Since each downstream station operates independently in generating flow control frames, it is possible for the same upstream station to receive multiple, overlapping pause commands. If an upstream station which is already paused receives subsequent flow control frames from the same downstream station that triggered the pause, the upstream station's pause timer is rewritten using the pause times in the successive flow control frames.Type: GrantFiled: November 1, 1999Date of Patent: September 9, 2003Assignee: International Business Machines CorporationInventors: Joel Erwin Geyer, Jeffrey James Lynch, Joseph Gerald McDonald
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Patent number: 6338102Abstract: A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.Type: GrantFiled: October 19, 1999Date of Patent: January 8, 2002Assignee: International Business Machines CorporationInventors: Henry Michael Garrett, William G. Holland, Joseph Franklin Logan, Joseph Gerald McDonald, John Kenneth Stacy
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Patent number: 6334162Abstract: A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.Type: GrantFiled: September 1, 2000Date of Patent: December 25, 2001Assignee: International Business Machines CorporationInventors: Henry Michael Garrett, William G. Holland, Joseph Franklin Logan, Joseph Gerald McDonald, John Kenneth Stacy
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Patent number: 6272564Abstract: A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.Type: GrantFiled: October 19, 1999Date of Patent: August 7, 2001Assignee: International Business Machines CorporationInventors: Henry Michael Garrett, William G. Holland, Joseph Franklin Logan, Joseph Gerald McDonald, John Kenneth Stacy
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Patent number: 6185207Abstract: A LAN adapter is implemented in the communication system to selectively exclude four bytes of the CRC value appended to an end of a frame's information field through the use of a configuration bit in a register. By programming this configuration bit to have a specific logic value, the four-bytes of the CRC value may be selectively copied, together with the data in the frame, into a destination computer system's main memory. Additionally, regardless of the setting of this configuration bit, the four-bytes of the CRC value will always be used to check the integrity of the data in the frame. Stated another way, the configuration bit will only affect whether the four-bytes of the CRC value will be transferred as part of the frame after the CRC check operation has been performed.Type: GrantFiled: June 19, 1997Date of Patent: February 6, 2001Assignee: International Business Machines CorporationInventors: Peter Anthony LaBerge, Joseph Franklin Logan, Joseph Gerald McDonald, Gregory Francis Paussa
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Patent number: 6163820Abstract: A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.Type: GrantFiled: October 19, 1999Date of Patent: December 19, 2000Assignee: International Business Machines CorporationInventors: Henry Michael Garrett, William G. Holland, Joseph Franklin Logan, Joseph Gerald McDonald, John Kenneth Stacy