Abstract: A radiation detection and counting system (2) includes a radiation detector element (5) for outputting a signal related to an energy of a radiation event received thereby and an amplifier (8) for amplifying the signal output by the detector element (5). A gain equalization circuit (10) adjusts the gain of the amplified output signal and a plurality of comparators (12) compare the gain adjusted amplified output signal to a like plurality of different valued threshold signals that are independently adjustable of each other A plurality of counters (20) is operative whereupon only the counter associated with the one comparator (12) that changes state in response to the peak of the gain adjusted amplified output signal exceeding the value of the trigger threshold signal thereof is incremented. A storage (24) stores the incremented value of each counter (20) accumulated over a sample time interval and data output logic circuit (26) transfers the stored accumulated counts out of the storage.

Abstract: A radiation detection and counting system (2) includes a radiation detector element (5) for outputting a signal related to an energy of a radiation event received thereby and an amplifier (8) for amplifying the signal output by the detector element (5). A gain equalization circuit (10) adjusts the gain of the amplified output signal and a plurality of comparators (12) compare the gain adjusted amplified output signal to a like plurality of different valued threshold signals that are independently adjustable of each other A plurality of counters (20) is operative whereupon only the counter associated with the one comparator (12) that changes state in response to the peak of the gain adjusted amplified output signal exceeding the value of the trigger threshold signal thereof is incremented. A storage (24) stores the incremented value of each counter (20) accumulated over a sample time interval and data output logic circuit (26) transfers the stored accumulated counts out of the storage.

Abstract: A radiation detection system includes a radiation detector and a DC/DC converter that induces an electric field in the radiation detector. A counter circuit outputs a pulse related to the energy of each incoming radiation event on the radiation detector. The peak amplitude of each pulse output by the counter circuit is converted into a digital equivalent value. A means for processing processes each digital equivalent value and counts a number of pulses output by the counter circuit over an interval of time. A port has one or more data lines connected to the means for processing and one or more power lines connected to the DC/DC converter. The port facilitates a connection to a host system which provides a single DC voltage to the DC/DC converter which converts the single DC voltage into a higher level voltage that induces the electric field in the radiation detector.

Abstract: A gamma ray camera A includes a crystal array S which includes a plurality of pixels 4 each of which outputs a pixel signal in response to receiving a gamma ray. A first circuit (6, 8, 10, 12, 14 and 22) outputs for each pixel 4 of the crystal array S, when a pixel signal output by the pixel 4 has a predetermined relation to a reference signal, a threshold signal related to the position of the pixel 4 in the crystal array S. A second circuit (18, 20, 24, 26, 28, 30 and 32) outputs a counter value for each pixel signal having a predetermined relation to its threshold signal. Lastly, a third circuit 34 accumulates for each pixel 4 of the crystal array S a count of the counter values output by the second circuit (18, 20, 24, 26, 28, 30 and 32) for the pixel 4.

Abstract: A gamma ray camera A includes a crystal array S which includes a plurality of pixels 4 each of which outputs a pixel signal in response to receiving a gamma ray. A first circuit (6, 8, 10, 12, 14 and 22) outputs for each pixel 4 of the crystal array S, when a pixel signal output by the pixel 4 has a predetermined relation to a reference signal, a threshold signal related to the position of the pixel 4 in the crystal array S. A second circuit (18, 20, 24, 26, 28, 30 and 32) outputs a counter value for each pixel signal having a predetermined relation to its threshold signal. Lastly, a third circuit 34 accumulates for each pixel 4 of the crystal array S a count of the counter values output by the second circuit (18, 20, 24, 26, 28, 30 and 32) for the pixel 4.