Patents by Inventor Joseph H. Fell, III

Joseph H. Fell, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6928560
    Abstract: A computer system incorporates distributed power control. In particular, the computer system comprises a power supply for providing at least one voltage, a power distribution system, and N boards, or modules (where N>1) coupled to the power supply via the power distribution system. Each board comprises a voltage regulator, which receives the voltage from the power supply and provides a regulated voltage to the board, and a processor for controlling the voltage regulator for varying the regulated voltage.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: August 9, 2005
    Assignee: Unisys Corporation
    Inventors: Joseph H. Fell, III, William Weil, Keith Mease, Gregory Corban
  • Patent number: 5721495
    Abstract: A quiescent test circuit for interfacing a high precision integrated circuit tester to a device under test (DUT). The quiescent test circuit is capable of supplying a high powered (V1) voltage supply to a DUT while the DUT's desired dynamics internal state is reached. At this point, the integrated circuit tester, sends an active select signal to the quiescent test circuit instantaneously which deselects the high-powered (V1) voltage supply to the DUT and selects the integrated circuit tester's parametric measurement unit low power (V4) voltage supply for powering the DUT. The integrated circuit tester, through its parametric measurement unit is capable of precisely measuring the very low quiescent current of the DUT, while powering the DUT.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: February 24, 1998
    Assignee: Unisys Corporation
    Inventors: Mark W. Jennion, Joseph H. Fell III, Paul H. Selby III, Joseph J. Scorsone
  • Patent number: 5652524
    Abstract: An improved load board design having a generic test circuit integrated into the load board capable of functioning with varying devices under test and requires little to no wiring. The test circuit is located in a fixed and optimal position of the load board with relation to the DUT. In a preferred embodiment, the test circuit is a quiescent test circuit for interfacing an integrated circuit tester to the DUT. The quiescent test circuit is capable of supplying high powered voltage to a DUT while the DUT's desired internal state is reached. At this point, the integrated circuit tester, sends an active select signal to the quiescent test circuit instantaneously deselecting the high-powered voltage supply to the DUT and selecting the integrated circuit tester's parametric measurement unit for powering the DUT. The integrated circuit tester, through a parametric measurement unit is capable of measuring the quiescent current of the DUT, while powering the DUT.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: July 29, 1997
    Assignee: Unisys Corporation
    Inventors: Mark W. Jennion, Joseph H. Fell, III, Paul H. Selby, III, Joseph J. Scorsone