Abstract: A memory controller for a computer system includes a first memory address bus and a second memory, address bus. The memory controller further includes circuitry that toggles one of the first and second memory address buses at a time. Because only one memory address bus is toggled at once, the first and second memory address buses can share power and ground pins, thereby reducing the number of power and ground pins on the memory controller.

Abstract: A power-up circuit for a multi-voltage chip having two or more electrostatic devices coupled in series between first and second power supply lines, with a first electrostatic device being coupled between a node and the second power supply line. The power-up circuit comprising a MOS transistor coupled between the first power supply line and the node. A voltage divider coupled between the first and second power supply lines controls the conductivity of the MOS transistor. An internal node of the voltage divider is coupled to the gate of the MOS transistor and the divider is configured such that the internal node rises in potential following power-up to regulate the conductivity of the MOS transistor. The MOS transistor changes from a high conducting state to a low conducting state responsive to an increase in potential of the second power supply line following power-up.

Abstract: A computer system device includes a data bus that transmits a plurality of bits of data, and a strobe line. The computer system device further includes a strobe signal generator that generates a strobe signal, and a variable delay device that couples the strobe signal generator to the strobe line. The variable delay device selectively delays the strobe signal.

Abstract: A circuit for testing the accuracy with which data is written from a first memory cell to a second memory cell including a shift register including master and slave portions, apparatus for placing data from the first memory cell into the master portion of the shift register and shifting the data into the slave portion of the shift register, apparatus for placing the data from the first memory cell into the second memory cell, apparatus for placing the data in the second memory cell back into the master portion of the shift register, and logic circuitry for testing the condition of the data in the master portion of the shift register against the condition of the data in the slave portion of the shift register to determine if the data has been correctly written into the second memory cell.

Abstract: A SRAM testing circuit utilized to assure that a voltage is at a sufficient level for accessing a memory cell including a pair of memory cells each including those elements necessary to duplicate the memory cells of an associated memory array, a circuit for providing alternating-valued input signals for writing to the pair of memory cells during each clock period at which a write operation may occur, apparatus for emulating the load provided to a bitline of an associated memory array, apparatus for applying the input signals to one of the pair of memory cells and applying the inverse of the input signals to the other of the pair of memory cells, apparatus for testing both the condition of each of the memory cells after the application of the input and inverse input signals against the condition of the signals provided to each of the cells to determine if each of the pair of memory cells has switched to the appropriate condition, and apparatus for generating a fail signal if either one of the pair of memory ce

Abstract: An arrangement for controlling the application of erase biasing voltages to the memory devices of a flash EEPROM memory array which arrangement precludes application of any erase biasing voltage until all of the devices are tested to determine which if any devices are programmed, and then allows application of erase bias voltages only to those blocks of the memory array which include devices which are programmed. In one embodiment, a power-on state machine which is used to read the state of the devices to initialize the array is used to test the condition of the array whenever an erase is desired and latching means are used with each block to preclude any erasing until it is determined that the block, in fact, includes programmed devices.

Abstract: A UPROM circuit including a pair of UPROM devices arranged to provide a first output level when one of the pair of UPROM devices is programmed and a second output level when the other of the UPROM devices is programmed. The UPROM circuit is programmed by circuitry which selectively provides programming voltages to each of the UPROM devices. Apparatus is provided for sensing the condition of the UPROM devices and feeding back signals for disabling the circuitry providing programming voltages whenever one of the UPROM devices is already programmed.

Abstract: A buffer circuit including a first N channel field effect transistor including a source terminal connected to ground, a gate terminal connected to a source of input signals, and a drain terminal; a W channel field effect transistor having a source terminal connected to the drain terminal of the N channel field effect transistor, a drain terminal connect to a source of varying voltage, and a gate terminal connected to its drain terminal; and an inverter having an input terminal connected to the drain terminal of the N channel transistor, and an output terminal.

Abstract: A mechanism to change the functionality of a state machine used to control operation of an EPROM device. The mechanism is programmed to generate logic level signals which are input to combinatorial logic used to implement the state machine to cause the state machine to operate with a predetermined number of wait states (typically on, two or three wait states) depending on the programming applied to the mechanism. The mechanism utilizes EPROM cells which are covered by a shield so that once programmed, they cannot be erased. The programming is performed after the part has been manufactured, but before shipment to a customer who, upon receipt of the part programs the EPROM in the usual manner. The programmed EPROM can then be erased nd reprogrammed without affecting the programming defining the number of wait states generated during operation of the state machine.

Abstract: A port expander for providing an external memory to be used with a microcontroller but recapturing the use of I/O ports which are lost due to the coupling of the memory. Two ports are coupled to the microcontroller for transfer of address and data information. An EPROM in the port expander provides the external memory while a special function register is used to couple data to and from two I/O ports. A configuration register provides programmability of which address values address the memory and which address values address the special function registers.

Abstract: A circuit for providing digital output signals carrying large amounts of currents without generating large transients at an output terminal connected to a load comprising apparatus for providing gradually increasing amounts of current of a first polarity to the output terminal, apparatus for providing gradually increasing amounts of current of a second polarity to the output terminal, apparatus for utilizing the apparatus for providing gradually increasing amounts of current of a first polarity to the output terminal to place the output terminal at a voltage level required for input signals, apparatus for providing a high impedance path to hold the output terminal at the voltage level required for input signals, and apparatus for disabling the apparatus for providing gradually increasing amounts of current of a first polarity and the apparatus for providing gradually increasing amounts of current of a second polarity to the output terminal.

Abstract: A circuit for providing digital output signals carrying large amounts of currents without generating large transients including apparatus for providing a first current path for providing current at a first rate and a first polarity, apparatus for providing a second current path for providing current at the first rate and the first polarity after a first delay, and apparatus for providing a third current path for providing current of the first polarity at a rate greater than the first rate and sufficient for a load connected thereto after a second delay equal to the first delay whereby the current available at the load has built to a level sufficient to sustain the load prior to the provision of the third current.

Abstract: Circuitry which when combined with an EPROM in a single integrated circuit for connection to a microprocessor which provides suitable signals utilized by the additional circuitry to provude faster access to the code or data stored in the EPROM than can be accomplished without such additional circuitry by providing zero wait state burst performance. A state machine is utilized to manage the interface between the microprocessor and the burst EPROM.

Abstract: A test mode enable circuit in which a test mode code is written to one latch and a test mode enable code is written to a second latch. The test mode enable code is compared to preprogrammed values stored in the enable circuit. When the test mode enable code matches the preprogrammed value, a presence of a high voltage activates a test mode enable signal for entering the test mode. The latched test mode code is then used to perform the desired test. Additionally a pulsewidth detector is used as a filter to permit only high voltages of a minimum pulsewidth duration to activate the enable signal thereby preventing false triggering.

Abstract: A CMOS output driver includes an n-channel low threshold device in series between a p-channel transistor and an output terminal. Under normal driver operation, the low threshold transistor drops essentially zero volts and is imperceptible in the circuit. However, under special mode conditions when high voltage is applied to the output terminal, the low threshold transistor stops conducting when the output terminal approaches Vcc, so that any further increase in the voltage at the output terminal cannot be applied to the drain of the p-channel transistor which can cause its failure.